1. 2017
  2. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Patent No. US 9,824,753, Priority date 21 Oct 2015

    Research output: Patent

  3. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Priority date 21 Oct 2015, Priority No. US 2017/0117041

    Research output: Patent

  4. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

    Sartor, A. L., Lorenzon, A. F., Carro, L., Kastensmidt, F., Wong, S. & Beck, A. C. S., 2017, In : ACM Journal on Emerging Technologies in Computing Systems. 13, 2, p. 13:1-13:21 21 p.

    Research output: Contribution to journalSpecial issueScientificpeer-review

  5. Exploring ILP and TLP on a Polymorphic VLIW Processor

    Brandon, A., Hoozemans, J., van Straten, J. & Wong, S., 2017, Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. Knoop, J., Karl, W., Schulz, M., Inoue, K. & Pionteck, T. (eds.). Cham: Springer, p. 177-189 13 p. (Lecture Notes in Computer Science ; vol. 10172).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Fast and accurate workload-level neural network based IC energy consumption estimation

    Cucu Laurenciu, N. & Cotofana, S., 2017, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. IEEE, p. 1-4 4 p. 7981598

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization

    Ren, S., Bertels, K. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 497-502 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Haar-based interconnect coding for energy effective medium/long range data transport

    Cucu Laurenciu, N. & Cotofana, S., 2017, Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. Alioto, M., Li, H., Becker, J., Schlichtmann, U. & Sridhar, R. (eds.). Piscataway, NJ: IEEE, p. 375-380 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL

    Houtgast, E., Sima, V. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 492-496 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

    Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Catthoor, F. & Cosemans, S., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 12, p. 3464-3472 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

    Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Kükner, H., Weckx, P., Raghavan, P. & Catthoor, F., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1444-1454 11 p., 7819518.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Interconnect Networks for Resistive Computing Architectures

    Du Nguyen, H. A., Xie, L., Yu, J., Taouil, M. & Hamdioui, S., 2017, 2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS). Danvers: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. LDPC-Based Adaptive Multi-Error Correction for 3D Memories

    Lefter, M., Voicu, G., Marconi, T., Savin, V. & Cotofana, S., 2017, 2017 IEEE International Conference on Computer Design (ICCD). IEEE, Vol. Piscataway. p. 265-268 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Low cost multi-error correction for 3D polyhedral memories

    Lefter, M., Marconi, T., Voicu, G. & Cotofana, S., 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures. IEEE, p. 13-18 6 p. 8053722

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Memristive devices: Technology, design automation and computing frontiers

    Barbareschi, M., Bosio, A., Du Nguyen, H. A., Hamdioui, S., Traiola, M. & Vatajelu, E. I., 2017, 2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS). Danvers: IEEE, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Memristor For Computing: Myth or Reality?

    Hamdioui, S., Kvatinsky, S., Cauwenberghs, G., Xie, L., Wald, N., Joshi, S., Elsayed, H. M., Corporaal, H. & Bertels, K., 2017, Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, p. 722-731 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Memristor based computation-in-memory architecture for big data

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. H03K; G06F, Priority date 7 Jul 2015, Priority No. WO 2017/007318

    Research output: Patent

  18. Mitigation of sense amplifier degradation using input switching

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Catthoor, F. & Dehaene, W., 2017, Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, p. 858-863 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Moving workloads to a better place: Optimizing computer architectures for data-intensive applications

    Vermij, E., 2017, 189 p.

    Research output: ThesisDissertation (TU Delft)

  20. On the Implementation of Computation-in-Memory Parallel Adder

    Du Nguyen, H. A., Xie, L., Taouil, M., Nane, R., Hamdioui, S. & Bertels, K., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 8, p. 2206 - 2219 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. On the Robustness of Memristor Based Logic Gates

    Xie, L., Du Nguyen, H. A., Yu, J., Taouil, M. & Hamdioui, S., 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Dietrich, M. & Novak, O. (eds.). Piscataway: IEEE, p. 158-163 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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