1. 2001
  2. Single electron encoded logic circuits

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, SAFE 2001: proceedings. Utrecht: STW Technology Foundation, p. 96-102 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Sparse matrix vector multiplication evaluation using the BBCS scheme

    Stathis, P., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 1. Y Manolopoulos & S Evripidou (eds.). S.l.: s.n., p. 40-49 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. Testing multi-port memories: theory and practice

    Hamdioui, S., 2001, S.l.: s.n.. 219 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  5. The MOLEN þµ-coded processor

    Vassiliadis, S., Wong, JSSM. & Cotofana, SD., 2001, Field-progammable logic and applications. G Goos & ... [et Al] (eds.). Berlin: Springer, p. 275-285

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  6. Transposition mechanism for sparse matrices on vector processors

    Stathis, P., Vassiliadis, S. & Cotofana, SD., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 641-645 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Variable length decoder implemented on a TriMedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 605-610 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. 2002
  9. 7/3 and 7/2 Counters implemented in single electron technology

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 344-350 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. A 2D adressing mode for multimedia applications

    Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  11. A CMOS flip-flop featuring embedded threshold logic functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 388-392 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  12. A Java-enabled DSP

    Glossner, CJ., Schulte, MJ. & Vassiliadis, S., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 307-327 19 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  13. A family of single electron static buffered Boolean logic

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 339-343 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  14. A flexible simulator for exploring hardware rasterizers

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. A full adder implementation using SET based linear threshold gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. Baric, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 665-669 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A hardware/software co-simulation environment for graphics accelerator development in ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 255-267 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  17. A low power 2D/3D graphics accelerator; A preliminary ISA

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 40 p.

    Research output: Book/ReportReportProfessional

  18. A low-power threshold logic family

    Padure, MD., Cotofana, SD., Vassiliadis, S., Dan, C. & Bodea, M., 2002, ICECS 2002; 9th IEEE International Conference on Electronica, Circuits and Systems. Piscatawy, NJ. USA: IEEE Society, p. 657-660 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. A peer-to-peer agent auction

    Ogston, EFYL. & Vassiliadis, S., 2002, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part I. Castelfranchi, C. & Johnson, WL. (eds.). New York: Association for Computing Machinery (ACM), p. 151-159 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. A proposal of a tile-based open GL compliant rasterization engine

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 123 p.

    Research output: Book/ReportReportProfessional

  22. A reconfigurable functional unit for TriMedia/CPU64

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliads, S. (eds.). Berlin: Springer, p. 224-242 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

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