1. A predictor-based power-saving policy for DRAM memories

    Thomas, G., Chandrasekar, K., Akesson, B., Juurlink, BHH. & Goossens, KGW., 2012, 15th Euromicro conference on digital system design. s.n. (ed.). s.n.: Euromicro, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A profiling framework for design space exploration in heterogeneous systems context

    Sigdel, K., Meeuws, RJ. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 363-368 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A proposal of a tile-based open GL compliant rasterization engine

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 123 p.

    Research output: Book/ReportReportProfessional

  5. A quantative prediction model for hardware/software partitioning

    Meeuws, RJ., Yankova, YD., Bertels, K., Gaydadjiev, GN. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 735-739 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A reconfigurable baseband for 2.5G/3G and beyond

    Glossner, CJ., Iancu, D., Hokenek, E. & Moudgill, M., 2003, WWC'2003 Proceedings; proceedings of 2003 world wireless congress. s.n. (ed.). San Francisco: Delson Group Inc., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. A reconfigurable beamformer for audio applications

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 2009 IEEE 7th symposium on application specific processors. s.n. (ed.). Piscataway: IEEE Society, p. 80-87 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A reconfigurable functional unit for TriMedia/CPU64

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliads, S. (eds.). Berlin: Springer, p. 224-242 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  9. A reconfigurable hardware based embedded scheduler for buffered crossbar switches

    Mhamdi, L., Kachris, C. & Vassiliadis, S., 2006, Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 143-149 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A reconfigurable perfect-hashing scheme for packet inspection

    Sourdis, I., Pnevmatikatos, DN., Wong, JSSM. & Vassiliadis, S., 2005, Proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005). Rissa, T., Wilton, S. & Leong, P. (eds.). IEEE Society, p. 644-647 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. A reconfigurable platform for multi-service edge routers

    Kachris, C. & Vassiliadis, S., 2007, 20th Symposium on integrated circuits and systems design. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 165-169 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. A reverse converter for the new 4-moduli set {2n+3, 2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international conference on electronics circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 113-116 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. A run-time modulo scheduling by using a binary translation mechanism

    Ferreira, R., Denver, W., Pereira, M., Quadros, J., Carro, L. & Wong, S., 2014, Proceedings - 2014 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Galuzzi, C. & Veidenbaum, AV. (eds.). Piscataway, NJ, USA: IEEE Society, p. 75-82 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. A run-time task migration scheme for an adjustable issue-slots multi-core processor

    Anjam, F., Kong, Q., Seedorf, RAE. & Wong, JSSM., 2012, 8th International symposium on applied reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme

    Berekovic, M. & Niggemeier, T., 2006, Embedded Computer Systems: Architectures, Modeling, and Simulation. Vassiliadis, S., Wong, S. & Hamalainen, TD. (eds.). Heidelberg: Springer, p. 289-298 10 p. (Lecture Notes in Computer Science; vol. 4017).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

    Lefter, M., Voicu, GR. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 425-428 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. A shared reconfigurable VLIW multiprocessor system

    Anjam, F., Wong, S. & Nadeem, MF., 2010, IPDPS 2010 conf. 24th IEEE intl. parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A sign bit only phase normalization for rotation and scale invariant template matching

    Ma, M., van Genderen, AJ. & Beukelman, P., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 641-646 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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