141 - 160 out of 1,563Page size: 20
  1. Article › Scientific › Peer-reviewed
  2. Microcode processing: positioning and directions

    Vassiliadis, S., Wong, JSSM. & Cotofana, SD., 2003, In : IEEE Micro. 23, 1, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Multi-core Platforms for Beamforming and Wave Field Synthesis

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, In : IEEE Transactions on Multimedia. 13, 2, p. 235-245 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Multi-target Regression Approach for Predictive Maintenance in Oil Refineries using Deep Learning

    Helmiriawan, H. & Al-Ars, Z., 2019, In : International Journal of Neural Networks and Advanced Applications. 6, p. 18-24 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Multimedia execution hardware accelerator

    Hakkennes, EA. & Vassiliadis, S., 2000, In : Journal of V LSISignal Processing. 28, 3, p. 221-234 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Multimedia rectangularly addressable memory

    Kuzmanov, GK., Gaydadjiev, GN. & Vassiliadis, S., 2006, In : IEEE Transactions on Multimedia. 8, 2, p. 315-322 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Multimedia rectangularly addressable memory

    Kuzmanov, GK., Gaydadjiev, GN. & Vassiliadis, S., 2005, In : IEEE Transactions on Multimedia.

    Research output: Contribution to journalArticleScientificpeer-review

  8. Multiple description coding for SNR scalable video transmission over unreliable networks

    Choupani, R., Wong, JSSM. & Tolun, MR., 2014, In : Multimedia Tools and Applications. 69, 3, p. 843-858 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Multiple description scalable coding for video transmission over unreliable networks

    Choupani, R., Wong, S. & Tolun, MR., 2009, In : Lecture Notes in Computer Science. 5657, p. 58-67 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Multiple-symbol parallel decoding for variable length codes

    Nikara, J., Vassiliadis, S., Takala, J. & Liuha, P., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 7, p. 676-685 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Multithreading on reconfigurable hardware: an architectural approach

    Zaykov, PG. & Kuzmanov, GK., 2012, In : Microprocessors and Microsystems. 36, 8, p. 695-704 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits

    Shah, A. P., Vishvakarma, S. K. & Cotofana, S., 1 Nov 2019, In : Microelectronics Reliability. 102, p. 1-8 8 p., 113391.

    Research output: Contribution to journalArticleScientificpeer-review

  13. New data-background sequences and their industrial evaluation for word-oriented random-access memories

    Hamdioui, S. & Reyes, JD., 2005, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 24, 6, p. 892-904 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

    Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 5, p. 1948-1959 12 p., 8574057.

    Research output: Contribution to journalArticleScientificpeer-review

  15. On chaos and neural networks: the backpropagation paradigm

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, DG., 2001, In : Artificial Intelligence Review: an international science and engineering journal. 15, 3, p. 165-187 23 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. On the Implementation of Computation-in-Memory Parallel Adder

    Du Nguyen, H. A., Xie, L., Taouil, M., Nane, R., Hamdioui, S. & Bertels, K., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 8, p. 2206 - 2219 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. On the integration of unicast and multicast cell scheduling in buffered crossbar switches

    Mhamdi, LL., 2009, In : IEEE Transactions on Parallel and Distributed Systems. 20, 6, p. 818-830 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Online hardware task scheduling and placement algorithm on partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 306-311 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. Online task scheduling for the FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2009, In : Lecture Notes in Computer Science. 5453, p. 216-230 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. OpenFPGA corelib core library interoperability effort

    Withlin, M., Poznanovic, D. & Kuzmanov, GK., 2008, In : Parallel Computing. 34, 4-5, p. 231-244 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. Opens and delay faults in CMOS RAM address decoder

    Hamdioui, S., Al-Ars, Z. & van de Goor, AJ., 2006, In : IEEE Transactions on Computers. 55, 12, p. 1630-1639 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

Previous 1...4 5 6 7 8 9 10 11 ...79 Next

ID: 19943