1. 2016
  2. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Alternative architectures toward reliable memristive crossbar memories

    Vourkas, I., Stathis, D., Sirakoulis, G. C. & Hamdioui, S., 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 206-217 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, In : SIGARCH Computer Architecture News. 44, 4, p. 38-43 6 p.

    Research output: Contribution to journalArticleScientific

  5. An Image Processing VLIW Architecture for Real-Time Depth Detection

    Iorga, D., Nane, R., Lu, Y., van Dalen, E. & Bertels, K., 2016, Proceedings - 28th IEEE International Symposium on Computer Architecture and High Performance Computing: SBAC-PAD 2016. Baldassin, A. (ed.). Piscataway: IEEE, p. 158-165 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability

    Yang, B., Grandhi, S., Spagnol, C., Popovici, E. & Cotofana, S., 2016, Proceedings - 27th Irish Signals and Systems Conference. Curran, K. (ed.). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

    Kritchallo, V., Braithwaite, B., Vermij, E., Bertels, K. & Al-Ars, Z., 2016, Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Hannig, F., Cardoso, J. M. P., Pionteck, T., Fey, D., Schröder-Preikschat, W. & Teich, J. (eds.). Cham: Springer, p. 251-262 12 p. (Lecture Notes in Computer Science; vol. 9367).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Boolean Logic Gate Exploration for Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2016, Proceedings - 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016. Danvers, MA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Brownian Circuits: Designs

    Lee, J., Peper, F., Cotofana, S., Naruse, M., Ohtsu, M., Kawazoe, T., Takahashi, Y., Shimokawa, T., Kish, L. B. & Kubota, T., 2016, In : International Journal of Unconventional Computing. 12, 5-6, p. 341-362 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. CIM100x: Computation in-Memory Architecture Based on Resistive Devices

    Hamdioui, S., Taouil, M., Du Nguyen, H. A., Haron, A., Xie, L. & Bertels, K., 2016, Proceedings of CNNA 2016: 15th International Workshop on Cellular Nanoscale and their Applications. Berlin: VDE, p. 95-96 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation

    Zandrahimi, M., Al-Ars, Z., Debaud, P. & Castillejo, A., 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Teich, J. (ed.). Piscataway, NJ: IEEE, p. 1018-1019 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Comparative BTI Analysis for Various Sense Amplifier Designs

    Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P. & Catthoor, F., 2016, Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Computational Challenges of Next Generation Sequencing Pipelines Using Heterogeneous Systems

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, p. 1-4. 4 p.

    Research output: Contribution to conferenceAbstractScientific

  14. CryoCMOS Hardware Technology: A Classical Infrastructure for a Scalable Quantum Computer

    Homulle, H., Visser, S., Patra, B., Ferrari, G., Prati, E., García Almudever, C., Bertels, K., Sebastiano, F. & Charbon, E., 2016, 2016 Proceedings of the ACM International Conference on Computing Frontiers. New York, NY: Association for Computing Machinery (ACM), p. 282-287 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Drift-free video coding for privacy protected video scrambling

    Choupani, R., Wong, S. & Tolun, M., 2016, 10th International Conference on Information, Communications and Signal Processing, ICICS 2015. Piscataway, NJ: IEEE, p. 1-5 5 p. 7459830

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Editorial Note on Memristor Models, Circuits and Architectures

    Sirakoulis, G. C. & Hamdioui, S., 2016, In : International Journal of Unconventional Computing. 12, 4, p. 247-250 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Error Correction Code protected Data Processing Units

    Cucu Laurenciu, N., Gupta, T., Savin, V. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. Exploration of Alternative GPU Implementations of the Pair-HMMs Forward Algorithm

    Ren, S., Bertels, K. & Al-Ars, Z., 2016, Proceedings 3rd International Workshop on High Performance Computing on Bioinformatics. p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

    Nguyen-Ly, T. T., Gupta, T., Pezzin, M., Savin, V., Declercq, D. & Cotofana, S., 2016, Proceedings - 19th Euromicro Conference on Digital System Design (DSD 2016). Kitsos, P. (ed.). Piscataway: IEEE, p. 230-237 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, Proceedings - 29th International Conference on Architecture of Computing Systems, ARCS 2016. Hannig, F., Cardoso, J. M. P., Pionteck, T., Fey, D., Schröder-Preikschat, W. & Teich, J. (eds.). Springer, p. 130-142 13 p. (Lecture Notes in Computer Science; vol. 9637).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Instruction cache aging mitigation through Instruction Set Encoding

    Gebregiorgis, A., Oboril, F., Tahoori, M. B. & Hamdioui, S., 2016, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. Wright, P., Mukhopadhyay, S. & Cline, B. (eds.). Piscataway, NJ: IEEE, p. 325-330 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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