1. (When) will CMPs hit the power wall?

    Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  2. 2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE Computer Society, p. 436-440 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  3. 2007 International conference on field programmable logic and applications

    Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

    Research output: Book/ReportBookProfessional

  4. 3-Tier reconfiguration model for FPGAs using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 504-509 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. 3D graphics benchmarks for low-power architectures

    Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 18-22 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. 3D graphics tile-based systolic scan-conversion

    Crisu, D., Vassiliadis, S., Cotofana, SD. & Liuha, P., 2004, Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on. Matthews, MB. (ed.). Piscataway: IEEE Society, p. 517-521 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. 3D stacked wide-operand adders: A case study

    Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE Computer Society, p. 133-141 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. 3D-COSTAR: a cost model for 3D stacked ICs

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE Computer Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. 3D-TV rendering on a multiprocessor system on a chip

    Li, X., van Eijndhoven, JTJ. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 271-282 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  11. 3D/ 2.5D stacked IC cost modeling and test flow selection

    Hamdioui, S., 2014, p. 1-1. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  12. 64-bit floating-point FPGA matrix multiplication

    Dou, Y., Vassiliadis, S., Kuzmanov, GK. & Gaydadjiev, GN., 2005, Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays (FPGA '05). s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 86-95 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. 7/3 and 7/2 Counters implemented in single electron technology

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 344-350 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  14. A 2D adressing mode for multimedia applications

    Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  15. A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

    Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  16. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. A 3D-audio reconfigurable processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  18. A CMOS flip-flop featuring embedded threshold logic functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 388-392 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  19. A CMOS semi-custom chip for mixed signal designs

    van Genderen, AJ., Cotofana, SD., de Graaf, G., Kaichouhi, A., Liedorp, J., Nouta, R., Pertijs, MAP. & Verhoeven, CJM., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 191-196 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  20. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms

    Ahmed, N., Bertels, K. & Al-Ars, Z., Dec 2016, 2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Tian, T., Jiang, Q., Liu, Y., Burrage, K., Song, J., Wang, Y., Hu, X., Morishita, S., Zhu, Q. & Wang, G. (eds.). Piscataway, NJ: IEEE, p. 1421-1428 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  22. A Computation-In-Memory Accelerator Based on Resistive Devices

    Du Nguyen, H. A., Yu, J., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 30 Sep 2019, (Accepted/In press) Proceedings of the International Symposium on Memory Systems. p. 1-14 14 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  23. A DfT architecture and tool flow for 3-D SICs with test data compression, embedded cores, and multiple towers

    Papameletis, C., Keller, B., Chickermane, V., Hamdioui, S. & Marinissen, EJ., 2015, In : IEEE Design & Test. 32, 4, p. 40-48 9 p.

    Research output: Contribution to journalArticleProfessional

  24. A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons

    Yu, J., Hogervorst, T. & Nane, R., 2017, GLSVLSI '17 Proceedings of the on Great Lakes Symposium on VLSI 2017 . New York: Association for Computing Machinery (ACM), p. 71-76 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  25. A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model

    Fang, J., Chen, J., Lee, J., Al-Ars, Z. & Hofstee, P., 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): Proceedings. IEEE, p. 335-335 1 p. 8735518

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  26. A Heterogeneous Quantum Computer Architecture

    Fu, X., Riesebos, L., Lao, L., García Almudever, C., Sebastiano, F., Versluis, R., Charbon, E. & Bertels, K., 2016, Proceedings of the ACM International Conference on Computing Frontiers, CF '16. New York: Association for Computing Machinery (ACM), p. 323-330 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  27. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  28. A Java-enabled DSP

    Glossner, CJ., Schulte, MJ. & Vassiliadis, S., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 307-327 19 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  29. A Locality-Aware Hash-Join Algorithm

    Fang, J., Hidders, J., Bertels, K., Lee, J. & Hofstee, P., 2016, p. 1-4. 4 p.

    Research output: Contribution to conferenceAbstractScientific

  30. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  31. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  32. A Non-Intrusive Online FPGA Test Scheme Using A Hardwired Network on Chip

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 351-359 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  33. A Novel Dynamic Task Scheduling Algorithm for Grid Networks with Reconfigurable Processors

    Nadeem, MF., Ostadzadeh, SA., Ahmadi, M., Nadeem, M. & Wong, JSSM., 2011, 5th HiPEAC Workshop on Reconfigurable Computing. s.n. (ed.). s.l.: HiPEAC, p. 21-30 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  34. A Novel Virtual Age Reliability Model for Time-toFailure Prediction

    Wang, Y. & Cotofana, SD., 2010, IEEE International Integrated Reliability Workshop Final Report. Young, C. & Geilenkeuser, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 102-105 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  35. A Reconfigurable Audio Beamforming Multi-Core Processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Symposium on Applied Reconfigurable Computing. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R. & El-Ghazawi, T. (eds.). Heidelberg: Springer, p. 3-14 12 p. (Lecture Notes in Computer Science; vol. 6578).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  36. A Simulation Framework for Reconfigurable Processors in Large-scale Distributed Systems

    Nadeem, MF., Ostadzadeh, SA., Nadeem, M., Wong, JSSM. & Bertels, KLM., 2011, International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Sheu, JP. & Wang, CL. (eds.). Piscataway: IEEE Society, p. 352-360 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  37. A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

    Yang, B., Popovici, E., Quille, M. A., Amann, A. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 79-84 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  38. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  39. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2011, Proceedings 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 818-822 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  41. A Uni¿ed Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits

    Wang, Y., Cotofana, SD. & Fang, L., 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures. Moritz, CA. & O'Connor, I. (eds.). Piscataway, NJ, USA: IEEE Society, p. 175-180 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  42. A VLIW softcore processor with dynamically adjustable issue-slots

    Anjam, F., Nadeem, M. & Wong, JSSM., 2010, 2010 intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  43. A cache architecture for counting bloom filters

    Ahmadi, M. & Wong, S., 2007, 15th International conference on networks. s.n. (ed.). Piscataway: IEEE Society, p. 218-223 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  44. A cache-based hardware accelerator for memory data movements

    Campos Soares Borrego, F., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  45. A case for hardware task management support for the StarSS programming

    Meenderinck, CH. & Juurlink, BHH., 2010, 13th Euromicro conf. on digital systems design, architectures, methods and tools. s.n. (ed.). Piscataway: IEEE Society, p. 347-354 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  46. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  47. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  48. A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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