1. Article › Scientific › Not peer-reviewed
  2. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  3. Agent-based social simulation in markets

    Bertels, KLM. & Boman, M., 2001, In : Electronic Commerce Research. 1, 1-2, p. 149-158 10 p.

    Research output: Contribution to journalArticleScientific

  4. An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, In : SIGARCH Computer Architecture News. 44, 4, p. 38-43 6 p.

    Research output: Contribution to journalArticleScientific

  5. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  6. Heterogeneous trading agents

    Neuberg, L. & Bertels, KLM., 2003, In : Complexity. 8, 5, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientific

  7. JAVA signal processing: FFTs with bitecodes

    Glossner, CJ., Thilo, J. & Vassiliadis, S., 2000, In : Concurrency: Practice and Experience. 10, 11-13, p. 1173-1178 6 p.

    Research output: Contribution to journalArticleScientific

  8. Link-time effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 2000, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 16, p. 503-511 9 p.

    Research output: Contribution to journalArticleScientific

  9. Multihierarchical intelligent simulation

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2001, In : Polytechnical University of Bucharest. Scientific Bulletin. Series C: Electrical Engineering and Computer Science. 63, 4, p. 15-24 10 p.

    Research output: Contribution to journalArticleScientific

  10. Parallel computer architecture and instruction-level parallelism

    Vassiliadis, S., Dimopoulos, N., Collard, JF. & Bode, A., 2003, In : Lecture Notes in Computer Science. p. 541-542 2 p.

    Research output: Contribution to journalArticleScientific

  11. Signed digit addition and related operations with threshold logic

    Cotofana, SD. & Vassiliadis, S., 2000, In : IEEE Transactions on Computers. 49, 3, p. 193-207 15 p.

    Research output: Contribution to journalArticleScientific

  12. The -Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, In : Journal of Lightwave Technology. 18, 8, p. 1049-1063 15 p.

    Research output: Contribution to journalArticleScientific

  13. Article › Scientific › Peer-reviewed
  14. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A control microarchitecture for fault-tolerant quantum computing

    Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

    Medeiros, G. C., Bolzani Poehls, L. M., Taouil, M., Luis Vargas, F. & Hamdioui, S., 2018, In : Microelectronics Reliability. 88-90, p. 355-359 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  23. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  25. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  26. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  27. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  28. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  29. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  31. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  32. A novel productivity-driven logic element for field-programmable devices

    Marconi, T., Bertels, KLM. & Gaydadjiev, GN., 2014, In : International Journal of Electronics. 101, 6, p. 731-762 32 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. A software-defined communications baseband design

    Glossner, CJ., Iancu, D., Lu, J., Hokenck, E. & Moudgill, M., 2003, In : IEEE Communications Magazine. 41, 1, p. 4-12 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

    van de Goor, AJ. & Tlili, IBS., 2003, In : IEEE Transactions on Computers. 52, 10, p. 1320-1330 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  35. A unified execution model for multiple computation models of streaming applications on a composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, In : Journal of Systems Architecture. 59, 10, part C, p. 1032-1046 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  36. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  37. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

    Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 61-73 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  38. Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

    Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

    Research output: Contribution to journalArticleScientificpeer-review

  39. Adaptive fault-tolerant architecture for unreliable technologies with heterogenous variability

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, In : IEEE Transactions on Nanotechnology. 11, 4, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. Addition related arithmetic operations via controlled transport of charge

    Cotofana, SD., Lageweg, CR. & Vassiliadis, S., 2005, In : IEEE Transactions on Computers. 54, 3, p. 243-256 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Addressing GPU on-chip shared memory bank conflicts using elastic pipeline

    Gou, C. & Gaydadjiev, GN., 2013, In : International Journal of Parallel Programming. 41, 3, p. 400-429 30 p.

    Research output: Contribution to journalArticleScientificpeer-review

  42. Alternative architectures toward reliable memristive crossbar memories

    Vourkas, I., Stathis, D., Sirakoulis, G. C. & Hamdioui, S., 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 206-217 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  43. An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1},

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 8, p. 1500-1503 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  44. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  45. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  46. An analysis of limited wavelength translation in regular all-optical WDM networks

    Sharma, A. & Varvarigos, EA., 2001, In : Journal of Lightwave Technology. 18, 12, p. 1606-1619 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  47. An analysis of oblivious and adaptive routing in optical networks with wavelength translation

    Lang, JP., Sharma, A. & Varvarigos, EA., 2001, In : IEEE - ACM Transactions on Networking. 9, 4, p. 503-517 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  48. An industrial evaluation of DRAM tests

    van de Goor, AJ., 2004, In : IEEE Design & Test of Computers. 21, 5, p. 430-440 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  49. Analog-to-digital converter based on single-electron tunneling transistors

    Hu, C., Cotofana, SD., Jiang, J. & Cai, Q., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 11, p. 1209-1213 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  50. Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics

    Veneman, WJ., de Sonneville, J., van der Kolk, KJ., Ordas, A., Al-Ars, Z., Meijer, AH. & Spaink, HP., 2015, In : Immunogenetics. 67, 3, p. 135-147 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  51. Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

    Wang, Y., Cotofana, SD. & Fang, L., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2521-2529 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

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