1. A reconfigurable functional unit for TriMedia/CPU64

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliads, S. (eds.). Berlin: Springer, p. 224-242 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  2. A reconfigurable hardware based embedded scheduler for buffered crossbar switches

    Mhamdi, L., Kachris, C. & Vassiliadis, S., 2006, Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 143-149 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A reconfigurable perfect-hashing scheme for packet inspection

    Sourdis, I., Pnevmatikatos, DN., Wong, JSSM. & Vassiliadis, S., 2005, Proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005). Rissa, T., Wilton, S. & Leong, P. (eds.). IEEE Society, p. 644-647 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A reconfigurable platform for multi-service edge routers

    Kachris, C. & Vassiliadis, S., 2007, 20th Symposium on integrated circuits and systems design. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 165-169 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A reverse converter for the new 4-moduli set {2n+3, 2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international conference on electronics circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 113-116 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A run-time modulo scheduling by using a binary translation mechanism

    Ferreira, R., Denver, W., Pereira, M., Quadros, J., Carro, L. & Wong, S., 2014, Proceedings - 2014 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Galuzzi, C. & Veidenbaum, AV. (eds.). Piscataway, NJ, USA: IEEE Society, p. 75-82 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A run-time task migration scheme for an adjustable issue-slots multi-core processor

    Anjam, F., Kong, Q., Seedorf, RAE. & Wong, JSSM., 2012, 8th International symposium on applied reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme

    Berekovic, M. & Niggemeier, T., 2006, Embedded Computer Systems: Architectures, Modeling, and Simulation. Vassiliadis, S., Wong, S. & Hamalainen, TD. (eds.). Heidelberg: Springer, p. 289-298 10 p. (Lecture Notes in Computer Science; vol. 4017).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

    Lefter, M., Voicu, GR. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 425-428 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. A shared reconfigurable VLIW multiprocessor system

    Anjam, F., Wong, S. & Nadeem, MF., 2010, IPDPS 2010 conf. 24th IEEE intl. parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. A sign bit only phase normalization for rotation and scale invariant template matching

    Ma, M., van Genderen, AJ. & Beukelman, P., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 641-646 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  14. A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, 19th IEEE International conference on embedded and real-time computing systems and applications. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. A software-defined communications baseband design

    Glossner, CJ., Iancu, D., Lu, J., Hokenck, E. & Moudgill, M., 2003, In : IEEE Communications Magazine. 41, 1, p. 4-12 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. A sparse VLIW instruction encoding scheme compatible with generic binaries

    Brandon, A., Hoozemans, J., Van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck, A. C. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers (IEEE), 7 p. 7393361

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A static low-power, high-peformance 32-bit carry skip adder

    Chirca, K., Schulte, M., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, Architectures, methods and tools. Selvaraj, H. (ed.). Piscataway: IEEE, p. 615-619 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. A sum of absolute differences implementation in FPGA hardware

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, EUROMICRO 2002; Proceedings of the 28th EUROMICRO Conference. Fernandez, M. (ed.). Piscataway, NJ. USA: IEEE Society, p. 183-188 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. A survey of autonomic computing systems

    Nami, MR. & Bertels, K., 2007, The third international conference on autonomic and autonomous systems. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A survey of coarse-grain reconfigurable architectures and CAD tools

    Theodoridis, G., Soudris, D. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 89-152 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  21. A survey of peer-to-peer networks

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2005, Proceedings of the SAFE & ProRISC 2005. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 570-577 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. A survey on low-power techniques for single and multicore systems

    Zandrahimi, M. & Al-Ars, Z., 2014, Proceedings 3rd International Conference on Context-Aware Systems and Applications. Mansoor, W., Maamar, Z. & Rabhi, F. (eds.). Ghent, Belgium: EAI, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

    van de Goor, AJ. & Tlili, IBS., 2003, In : IEEE Transactions on Computers. 52, 10, p. 1320-1330 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. A systolic architecture for the Smith-Waterman algorithm with high performance cell design

    Hasan, L., Khawaya, YM. & Bais, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 35-42 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A taxonomy of custom computing machines

    Sima, M., Vassiliadis, S., Cotofana, SD., van Eijndhoven, JTJ. & Vissers, K., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 71-77 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  26. A taxonomy of field-programmable custom computing machines

    Sima, M., Vassiliadis, S. & Cotofana, SD., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 299-378 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  27. A turnstile based single electron memory element

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, SAFE 2001: proceedings. Utrecht: STW Technology Foundation, p. 103-108 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. A two-phase practical parallel algorithm for construction of huffman codes

    Ostadzadeh, SA., Maryam Elahi, B., Tabrizi, ZZ., Amir Moulavi, M. & Bertels, K., 2007, 2007 intl. conf. on Parallel and distributed processing techniques and applicationss. Arabnia HR (ed.). USA: CSREA Press, p. 284-291 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. A unified addition structure for moduli set 2n-1, 2n, 2n+1 based on a novel RNS representation

    Timarchi, S., Fazlali, M. & Cotofana, SD., 2010, ICCD 2010. s.n. (ed.). Piscataway: IEEE Society, p. 247-252 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. A unified execution model for multiple computation models of streaming applications on a composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, In : Journal of Systems Architecture. 59, 10, part C, p. 1032-1046 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  31. A user-level library for fault tolerance on shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 15th IEEE symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

    Celinski, P., Cotofana, SD. & Abbott, D., 2003, Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 73-80 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors

    Mei, B., Berekovic, M. & Mignolet, J-Y., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 255-298 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  35. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

    Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 61-73 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  36. ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications

    Al-Ars, Z., van der Vlugt, S., Jääskeläinen, P. & van der Linden, F., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 1-7 7 p.

    Research output: Contribution to journalEditorialScientificpeer-review

  37. ALU Augmentation for MPEG-4 repetitive padding

    Kuzmanov, GK. & Vassiliadis, S., 2002, MPCS'02 Proceedings of the 2002 Euromicro conference on Massively-Parallel Computing Systems. Fort Collins, Col. USA: National Technological University Press, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  38. Accelarating color space conversion using extended subwords and the matrix register file

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2006, Eighth IEEE international Symposium on multimedia. Piscataway: IEEE Society, p. 37-44 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. Accelerating DNA Variant Calling Algorithms on High Performance Computing Systems

    Ren, S., 2018, 83 p.

    Research output: ThesisDissertation (TU Delft)

  40. Accelerating a geometrical approximated PCA algorithm using AVX2 and CUDA

    Machidon, A. L., Machidon, O. M., Ciobanu, C. B. & Ogrutan, P. L., 2020, In : Remote Sensing. 12, 12, 29 p., 1918.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Accelerating complex brain-model simulations on GPU platforms

    Nguyen, HAD., Al-Ars, Z., Smaragdos, G. & Strydis, C., 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ, USA: IEEE Society, p. 974-979 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Accelerating the secure remote password protocol using reconfigurable hardware

    Groen, PT., Hämäläinen, P., Juurlink, BHH. & Hämäläinen, T., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 471-480 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Acceleration of Bioinformatics Sequence Alignment - A Hardware Perspective

    Hasan, L., 2011, Germany: LAP LAMBERT Academic Publishing. 132 p.

    Research output: Book/ReportBookScientific

  44. Acceleration of Smith-Waterman using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Acceleration of biological sequence alignment using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 233-237 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

    Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. Achieving fanout capabilities in single electron encoded logic networks

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 2. Piscataway: IEEE Society, p. 1383-1386 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

    Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

    Research output: Contribution to journalArticleScientificpeer-review

  49. Adapting communication for adaptable processors: a multi-axis reconfiguration approach

    Santos, PC., Nazar, GL., Anjam, F. & Wong, JSSM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs

    Monteiro OliveiraCortez, AM., van der Leest, V., Maes, R., Schrijen, GJ. & Hamdioui, S., 2013, IEEE International symposium on hardware-oriented security and trust. s.n. (ed.). Piscataway: IEEE Society, p. 35-40 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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