1. 2013
  2. Run-time slack distribution for real-time data-flow applications on embedded MPSoC

    Zaykov, PG., Kuzmanov, GK., Molnos, AM. & Goossens, KGW., 2013, 16th Euromicro conference on digital system design. s.n. (ed.). Piscataway: IEEE Society, p. 39-47 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Separable 2D convolution with polymorphic register files

    Ciobanu, CB. & Gaydadjiev, GN., 2013, 26th International conference on architecture of computing systems. Hochberger et al (ed.). Berlin: Springer, p. 317-328 12 p. (Lecture Notes in Computer Science; vol. 7767).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

    Chandrasekar, K., Weis, C., Akesson, B., Wehn, N. & Goossens, KGW., 2013, Proceedings 2013 Design, Automation & Test in Europe conference & exhibition. Preas, K. (ed.). Leuven, Belgium: EDAA, p. 236-241 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. TLM modelling of 3D stacked wide I/O DRAM Subsystems

    Jung, M., Weis, C., Wehn, N. & Chandrasekar, K., 2013, Proceedings 5th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. Palermo, G., Gracia Perez, D. & Castrillon et al, J. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. The CompSOC design flow for virtual execution platforms

    Goossens, SLM., Akesson, B., Koedam, M., Beyranvand Nejad, A., Nelson, AT. & Goossens, KGW., 2013, 10th FPGAworld Conference. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. The genetic heterogeneity and mutational burden of engineered melanomas in zebrafish models

    Yen, J., White, RM., Wedge, DC., van Loo, P., de Ridder, J., Capper, A., Richardson, J., Jones, D., Raine, K., Watson, IR., Wu, C-J., Cheng, J., Martincorena, I., Nik-Zainal, S., Mudie, LJ., Moreau, Y., Marshall, J., Ramakrishna, M., Tarpey, P., Shlien, A. & 20 othersWhitmore, I., Gamble, S., Latimer, C., Langdon, E., Kaufman, C., Dovey, M., Taylor, A., Menzies, A., Mclaren, S., O Meara, S., Butler, A., Teague, J., Lister, J., Chin, L., Campbell, PJ., Adams, DJ., Zon, LI., Patton, EE., Stemple, DL. & Futreal, AP., 2013, In : Genome Biology (Online). 14, R113, p. 1-14 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. Throughput analysis and voltage-frequency island partitioning for streaming applications under process variation

    Mirzoyan, D., Stuijk, S., Akesson, B. & Goossens, KGW., 2013, Proceedings 2013 IEEE 11th Symposium on Embedded Systems for Real-Time Multimedia. Stefanov, T. & Palesi et al, M. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

    Voicu, GR. & Cotofana, SD., 2013, 9th ACM/IEEE International Symposium on Nanoscale Architectures). s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Towards variation-aware system-level power estimation of DRAMs: an empirical approach

    Chandrasekar, K., Weis, C., Akesson, B., Wehn, N. & Goossens, KGW., 2013, 50th Design Automation Conference. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Ultra low power NEMFET based logic

    Enachescu, M., Lefter, M., Bazigos, A., Ionescu, A. & Cotofana, SD., 2013, IEEE International symposium on circuits and systems. Piscataway: IEEE Society, p. 566-569 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Using 3D-COSTAR for 2.5D test cost optimization

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2013, IEEE International 3D Systems Integration Conference. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. VASILE: a reconfigurable vector architecture for instruction level frequency scaling

    Petrica, L., Codreanu, V. & Cotofana, SD., 2013, 12th IEEE low voltage low power conference. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Variability and reliability analyses in SRAM decoder

    Seyab, MSK. & Hamdioui, S., 2013, 4th Workshop on design for reliability. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow

    Goossens, KGW., Pereira de Azevedo Filho, AP., Chandrasekar, K., Mirzoyan, D., Molnos, AM., Beyranvand Nejad, A. & Nelson, AT., 2013, In : SIGBED Review. 10, 3, p. 23-34 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. 2012
  17. 3D-COSTAR: a cost model for 3D stacked ICs

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2012, Conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. A lightweight speculative and predicative scheme for hardware execution

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. A novel flit serialization strategy to utilize partially faulty links in networks-on-chip

    Chen, C. & Lu, Y., 2012, 2012 Sixth IEEE/ACM international symposium on networks-on-chip. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. A predictor-based power-saving policy for DRAM memories

    Thomas, G., Chandrasekar, K., Akesson, B., Juurlink, BHH. & Goossens, KGW., 2012, 15th Euromicro conference on digital system design. s.n. (ed.). s.n.: Euromicro, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. A run-time task migration scheme for an adjustable issue-slots multi-core processor

    Anjam, F., Kong, Q., Seedorf, RAE. & Wong, JSSM., 2012, 8th International symposium on applied reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A user-level library for fault tolerance on shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 15th IEEE symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Adapting communication for adaptable processors: a multi-axis reconfiguration approach

    Santos, PC., Nazar, GL., Anjam, F. & Wong, JSSM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Adaptive fault-tolerant architecture for unreliable technologies with heterogenous variability

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, In : IEEE Transactions on Nanotechnology. 11, 4, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. Analyzing combined impacts of parameter variations and BTI in nano-scale logical gates

    Seyab, MSK. & Hamdioui, S., 2012, 1st Workshop on manufacturable and dependable multicore architectures at nanoscale. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Architecture and design flow for a debug event distribution interconnect

    Pereira de Azevedo Filho, AP., Vermeulen, B. & Goossens, KGW., 2012, 30th IEEE International conference on computer design. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Area constraint propagation in high level synthesis

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on field-programmable technology. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. BTI Impacts on logical gates in nano-scale CMOS technology

    Seyab, MSK., Hamdioui, S., Kukner, H., Catthoor, F. & Raghavan, P., 2012, 15th IEEE Symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Communication-aware HW/SW co-design for heterogeneous multicore platforms

    Ashraf, I., Ostadzadeh, SA., Meeuws, RJ. & Bertels, KLM., 2012, 10th International workshop on dynamic analysis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Comparative BTI analysis in nano-scale circuits lifetime

    Seyab, MSK., Hamdioui, S. & Catthoor, F., 2012, 4th Workshop on design for reliability. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. Comparative analysis of soft and hard on-chip interconnects for FPGAs

    Hur, JY., Goossens, KGW., Mhamdi, L. & Wahlah, MA., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  35. Compiler assisted runtime adaption

    Sima, VM., 2012, Delft. 129 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  36. Conclusion: multi-core processor architectures are here to stay.

    Bertels, KLM., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 229-231 234 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  37. Context aware slope based transistor-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  38. Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

    Hur, JY., Stefanov, TP., Wong, JSSM. & Goossens, KGW., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 59-68 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  39. DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

    Nane, R., Sima, VM., Olivier, B., Meeuws, RJ., Yankova, YD. & Bertels, KLM., 2012, 22nd International conference on field programmable logic and applications. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms

    Molnos, AM., Beyranvand Nejad, A., Nguyen, BT., Cotofana, SD. & Goossens, KGW., 2012, 15th Intl.Workshop on software and compilers for embedded systems. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Degradation stochastic resonance (DSR) in AD-AVG architectures

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, 12th IEEE International conference on nanotechnology. s.n. (ed.). New York: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Design of a pipelined and parameterized VLIW processor: r-VEX v.2.0

    Seedorf, RAE., Anjam, F., Brandon, AAC. & Wong, JSSM., 2012, 6th HiPEAC workshop on reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. DetLock: portable and efficient deterministic execution for shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 5th International workshop on multi-core computing systems. s.n. (ed.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. DfT schemes for resistive open defects in RRAMs

    Haron, NZB. & Hamdioui, S., 2012, Design, automation & test in Europe conference & exhibition. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2012, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 59, 2, p. 636-657 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  46. Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints

    Nelson, AT., Molnos, AM., Beyranvand Nejad, A., Mirzoyan, D., Cotofana, SD. & Goossens, KGW., 2012, Workshop on embedded and cyber-physical systems education. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. Energy efficient wireless attitude determination system for spacecraft

    Gaydadjiev, GN., Amini, R. & Gill, EKA., 2012, Patent No. 2005664, Priority date 14 May 2012

    Research output: PatentOther research output

  48. Evaluation of different task scheduling policies in multi-core systems with recon¿gurable hardware

    Shahsavari, M., Al-Ars, Z. & Bertels, KLM., 2012, 8th International summer school on advanced computer architecture and compilation for high-performance and embedded systems. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Exploring test opportunities for memory and interconnects in 3D ICs

    Taouil, M., Lefter, M. & Hamdioui, S., 2012, International design & test symposium. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Extensions of the hArtes tool chain

    Meeuws, RJ., Ostadzadeh, SA., Nawaz, Z., Lu, Y., Thomas, TM., Sabeghi, M., Sima, VM. & Sigdel, K., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 193-227 234 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  51. Fault tolerance on multicore processors using deterministic multithreading

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, International design & test symposium. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Field programmable gate arrays with hardwired networks on chip

    Wahlah, MA., 2012, Delft. 229 p.

    Research output: ThesisDissertation (TU Delft)Scientific

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