1. 2004
  2. Low-cost capacitive personnel detector

    Aguilar Cardenas, RN., Roelofsz, MC., Kerkvliet, HMM., van de Ven, RJ. & Meijer, GCM., 2004, Proceedings of the thirteenth international scientific and applied science conference electronics ET'2004. Sofia, Bulgaria: Technical University of Sofia, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  3. 2003
  4. A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

    Celinski, P., Cotofana, SD. & Abbott, D., 2003, Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 73-80 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Area efficient, High speed parallel counter circuits using charge recycling threshold logic

    Celinski, P., Abbott, D. & Cotofana, SD., 2003, ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems. Piscataway: IEEE Society, p. 233-236 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Coherent interconnect/substrate modeling using SPACE - an experimental study

    Schrik, E., van Genderen, AJ. & van der Meijs, NP., 2003, ESSDERC 2003 33rd European solid-state device research conference. Franca, J. & Freitas, P. (eds.). Piscataway: IEEE Society, p. 585-588 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates

    Celinski, P., Cotofana, SD. & Abbott, D., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 43-48 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. State-of-the-art in CMOS threshold-logic VSLI gate implementations and applications

    Celinski, P., Cotofana, SD., López, JF., Al-Sarawi, S. & Abbott, D., 2003, Microtechnologies for the new millenium 2003. s.n. (ed.). Bellingham: SPIE, p. 53-64 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. 2002
  10. Threshold logic parallel counters for 32-bit multipliers

    Celinski, P., Cotofana, SD. & Abbott, D., 2002, International symposium on smart materials, Nano-, and micro-smart systems 2002. s.n. (ed.). Belingham: SPIE, p. 205-214 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. 2001
  12. Combined BEM/FEM resistance modeling of straified substrates with layout-dependent doping patterns in the top layer

    Schrik, E., van Genderen, AJ. & van der Meijs, NP., 2001, SAFE - ProRISC - SeSens 2001: proceedings CD-ROM. Utrecht: STW Technology Foundation, p. 598-604 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Modeling capacitive coupling effects via the substrate

    van Genderen, AJ., van der Meijs, NP. & Schrik, E., 2001, SAFE - ProRISC - SeSens proceedings: CD-ROM. Utrecht: STW Technology Foundation, p. 366-370 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. SPACE application note 2001-1: modeling layout-dependent substrate doping variations

    van Genderen, AJ., de Graaf, S. & van der Meijs, NP., 2001, S.l.: s.n. 12 p.

    Research output: Book/ReportReportProfessional

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