1. 2018
  2. A low-cost BRAM-Based function reuse for configurable soft-core processors in FPGAs

    Becker, P. H. E., Sartor, A. L., Brandalero, M., Trevisan Jost, T., Wong, S., Carro, L. & Beck, A. C., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer Verlag, p. 499-510 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability

    Souza, J. D., Sartor, A. L., Carro, L., Rutzig, M. B., Wong, S. & Beck, A. C. S., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer Verlag, p. 367-378 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-issue VLIW Processor

    Sartor, A. L., Becker, P. H. E., Hoozemans, J., Wong, S. & Beck, A. C. S., 2018, In : IEEE Transactions on Multi-Scale Computing Systems. 4, 3, p. 327-339 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores

    Erichsen, A. G., Sartor, A. L., Souza, J. D., Pereira, M. M., Wong, S. & Beck, A. C. S., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer Verlag, p. 231-242 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. 2017
  7. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

    Sartor, A. L., Lorenzon, A. F., Carro, L., Kastensmidt, F., Wong, S. & Beck, A. C. S., 2017, In : ACM Journal on Emerging Technologies in Computing Systems. 13, 2, p. 13:1-13:21 21 p.

    Research output: Contribution to journalSpecial issueScientificpeer-review

  8. 2016
  9. Adaptive ILP Control to increase Fault Tolerance for VLIW Processors

    Sartor, A. L., Wong, S. & Beck, A. C. S., Jul 2016, Application-specific Systems, Architectures and Processors (ASAP), 2016 IEEE 27th International Conference on. London, UK, 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. 2015
  11. A sparse VLIW instruction encoding scheme compatible with generic binaries

    Brandon, A., Hoozemans, J., Van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck, A. C. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 7393361

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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