1. 2019
  2. A sparse spin qubit array with integrated control electronics

    Boter, J. M., Dehollain, J. P., van Dijk, J. P. G., Hensgens, T., Versluis, R., Clarke, J. S., Veldhorst, M., Sebastiano, F. & Vandersypen, L. M. K., 2019, 2019 IEEE International Electron Devices Meeting, IEDM 2019. Takayanagi, M. (ed.). Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-December. 4 p. 8993570

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Benefits and challenges of designing cryogenic CMOS RF circuits for quantum computers

    Mehrpoo, M., Patra, B., Gong, J., T Hart, P. A., Van Dijk, J. P. G., Homulle, H., Kiene, G., Vladimirescu, A., Sebastiano, F., Charbon, E. & Babaie, M., 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ, USA: IEEE, 5 p. 8702452

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Impact of Classical Control Electronics on Qubit Fidelity

    Van Dijk, J. P. G., Kawakami, E., Schouten, R. N., Veldhorst, M., Vandersypen, L. M. K., Babaie, M., Charbon, E. & Sebastiano, F., 2019, In : Physical Review Applied. 12, 4, 20 p., 044054.

    Research output: Contribution to journalArticleScientificpeer-review

  5. SPINE (SPIN Emulator)-A Quantum-Electronics Interface Simulator

    Dijk, J. V., Vladimirescu, A., Babaie, M., Charbon, E. & Sebastiano, F., 2019, Proceedings - 2019 8th International Workshop on Advances in Sensors and Interfaces, IWASI 2019. De Venuta, D. (ed.). Institute of Electrical and Electronics Engineers (IEEE), p. 23-28 8791334

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Scalable read-out schemes for qubits

    Sebastiano, F., 2019, In : Nature Electronics. 2, 6, p. 215-216 2 p.

    Research output: Contribution to journalArticleScientific

  7. The electronic interface for quantum processors

    van Dijk, J. P. G., Charbon, E. & Sebastiano, F., 2019, In : Microprocessors and Microsystems. 66, p. 90-101

    Research output: Contribution to journalArticleScientificpeer-review

  8. Wakeup Timer Using Bang-Bang Digital-Intensive Frequency Locked-Loop

    Ding, M., Sebastiano, F., Liu, Y-H. & Zhou, Z., 2019, Patent No. US 10,491,224, Priority date 27 Feb 2018

    Research output: Patent

  9. Wakeup Timer Using Bang-Bang Digital-Intensive Frequency Locked-Loop

    Ding, M., Sebastiano, F., Liu, Y-H. & Zhou, Z., 2019, Priority date 27 Feb 2018, Priority No. US 2019/0268007

    Research output: Patent

  10. 2018
  11. A 0.7-V 0.43-pJ/cycle Wakeup Timer based on a Bang-bang Digital-Intensive frequency-Locked-Loop for IoT Applications

    Ding, M., Zhou, Z., Liu, Y-H., Traferro, S., Bachmann, C., Philips, K. & Sebastiano, F., Feb 2018, In : IEEE Solid State Circuits Letters. 1, 2, p. 30-33 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

    Homulle, H., Song, L., Charbon, E. & Sebastiano, F., 24 Jan 2018, In : IEEE Journal of the Electron Devices Society. 6, 1, p. 263-270 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

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