1. 3D stacked wide-operand adders: A case study

    Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE Computer Society, p. 133-141 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  2. A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

    Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

    Lefter, M., Voicu, GR. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 425-428 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Advanced NEMS-based power management for 3D stacked integrated circuits

    Enachescu, M., Voicu, GR. & Cotofana, SD., 2010, 2010 Intl. conf. on energy aware computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1},

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 8, p. 1500-1503 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. An efficient FPGA design of reverse converter for the moduli set {2n+2, 2n+1, 2n}

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2010, Advanced computer architecture and compilation for high-performance and embedded systems. s.n. (ed.). s.l.: s.n., p. 117-120 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  8. Energy effective 3D stacked hybrid NEMFET-CMOS caches

    Lefter, M., Enachescu, M., Voicu, GR. & Cotofana, SD., 2014, Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures. Klein, JO. & Moritz, CA. (eds.). Piscataway, NJ, USA: IEEE Society, p. 151-156 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. High-performance, Cost-effective 3D Stacked Wide-Operand Adders

    Voicu, G. R. & Cotofana, S. D., 4 Aug 2016, In : IEEE Transactions on Emerging Topics in Computing. 5, 2, p. 179-192 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Is 3D integration the way to future dependable computing platforms?

    Safiruddin, S., Borodin, DV., Lefter, M., Voicu, GR. & Cotofana, SD., 2012, 3th International conference on optimization of electrical and electronic equipment. s.n. (ed.). New York: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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