1. Article › Scientific › Peer-reviewed
  2. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Context aware slope based transistor-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Critical transistors nexus based circuit-level aging assessment and prediction

    Cucu Laurenciu, N. & Cotofana, SD., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2512-2520 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Graphene Nanoribbon Based Complementary Logic Gates and Circuits

    Jiang, Y., Cucu Laurenciu, N., Wang, H. & Cotofana, S. D., 2019, In : IEEE Transactions on Nanotechnology. 18, p. 287-298 12 p., 8666174.

    Research output: Contribution to journalArticleScientificpeer-review

  6. On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

    Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 5, p. 1948-1959 12 p., 8574057.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Conference contribution › Scientific › Peer-reviewed
  8. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

    Cucu Laurenciu, N. & Cotofana, SD., 2013, 21st IFIP/IEEE international conference on very large scale integration. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Atomistic-level hysteresis-aware graphene structures electron transport model

    Wang, H., Cucu Laurenciu, N., Jiang, Y. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2019-May. p. 1-5 5 p. 8702106

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. Complementary arranged graphene nanoribbon-based boolean gates

    Jiang, Y., Laurenciu, N. C. & Cotofana, S., 17 Jul 2018, Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Cotofana, S. & Sirakoulis, G. C. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 51-57 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  12. Error Correction Code protected Data Processing Units

    Cucu Laurenciu, N., Gupta, T., Savin, V. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 37-42 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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