1. 2019
  2. On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

    Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers. PP, 99, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. 2018
  4. Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

    Enachescu, M., Lefter, M., Voicu, G. & Cotofana, S., 2018, In : IEEE Transactions on Emerging Topics in Computing. 6, 2, p. 184-199 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps

    Jiang, Y., Cucu Laurenciu, N. & Cotofana, S., 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS) : Proceedings. Piscataway, NY: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. 2017
  7. Fast and accurate workload-level neural network based IC energy consumption estimation

    Cucu Laurenciu, N. & Cotofana, S., 2017, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. IEEE, p. 1-4 4 p. 7981598

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. Haar-based interconnect coding for energy effective medium/long range data transport

    Cucu Laurenciu, N. & Cotofana, S., 2017, Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. Alioto, M., Li, H., Becker, J., Schlichtmann, U. & Sridhar, R. (eds.). Piscataway, NJ: IEEE, p. 375-380 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. LDPC-Based Adaptive Multi-Error Correction for 3D Memories

    Lefter, M., Voicu, G., Marconi, T., Savin, V. & Cotofana, S., 2017, 2017 IEEE International Conference on Computer Design (ICCD). IEEE, Vol. Piscataway. p. 265-268 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Low cost multi-error correction for 3D polyhedral memories

    Lefter, M., Marconi, T., Voicu, G. & Cotofana, S., 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures. IEEE, p. 13-18 6 p. 8053722

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

    Chen, C., Fu, Y. & Cotofana, S., 2017, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 36, 2, p. 285-298 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. 2016
  13. High-performance, Cost-effective 3D Stacked Wide-Operand Adders

    Voicu, G. R. & Cotofana, S. D., 4 Aug 2016, In : IEEE Transactions on Emerging Topics in Computing. 5, 2, p. 179-192 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

    Yang, B., Popovici, E., Quille, M. A., Amann, A. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 79-84 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Previous 1 2 3 4 5 6 7 8 ...25 Next

ID: 117900