A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Robert Bogdan Staszewski

doi:10.1109/VLSIC.2018.8502274

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

12 Citations (Scopus)

Abstract

All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.

Original language	English
Title of host publication	2018 Symposium on VLSI Circuits Digest of Technical Papers
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	183-184
Number of pages	2
Volume	2018-June
ISBN (Electronic)	978-1-5386-4214-6
DOIs	https://doi.org/10.1109/VLSIC.2018.8502274
Publication status	Published - 22 Oct 2018
Externally published	Yes
Event	2018 Symposia on VLSI Technology and Circuits: 2018 VLSI Technology Symposium - 2018 VLSI Circuits - Hilton Hawaiian Village, Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Conference

Conference	2018 Symposia on VLSI Technology and Circuits
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

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10.1109/VLSIC.2018.8502274

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@inproceedings{fcc56d78212b4a78a8685b9d23044176,

title = "A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW",

abstract = "All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.",

author = "Tsung-Hsien Tsai and Ruey-Bin Sheen and Chih-Hsien Chang and Staszewski, {Robert Bogdan}",

year = "2018",

month = oct,

day = "22",

doi = "10.1109/VLSIC.2018.8502274",

language = "English",

volume = "2018-June",

pages = "183--184",

booktitle = "2018 Symposium on VLSI Circuits Digest of Technical Papers",

publisher = "IEEE",

address = "United States",

note = "2018 Symposia on VLSI Technology and Circuits : 2018 VLSI Technology Symposium - 2018 VLSI Circuits ; Conference date: 18-06-2018 Through 22-06-2018",

}

Tsai, T-H, Sheen, R-B, Chang, C-H & Staszewski, RB 2018, A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. in 2018 Symposium on VLSI Circuits Digest of Technical Papers. vol. 2018-June, 8502274, IEEE, Piscataway, NJ, pp. 183-184, 2018 Symposia on VLSI Technology and Circuits, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIC.2018.8502274

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. / Tsai, Tsung-Hsien; Sheen, Ruey-Bin; Chang, Chih-Hsien et al.
2018 Symposium on VLSI Circuits Digest of Technical Papers. Vol. 2018-June Piscataway, NJ: IEEE, 2018. p. 183-184 8502274.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Tsai, Tsung-Hsien

AU - Sheen, Ruey-Bin

AU - Chang, Chih-Hsien

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AB - All-digital PLLs (ADPLL) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization (Q) noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLL) do not exhibit Q-noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain. We propose a hybrid-PLL in 7nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL with a periodical phase realignment by the reference clock. It covers 0.2GHz-4GHz with 0.619ps integrated jitter and settles in 0.6us.

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M3 - Conference contribution

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VL - 2018-June

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EP - 184

BT - 2018 Symposium on VLSI Circuits Digest of Technical Papers

PB - IEEE

CY - Piscataway, NJ

T2 - 2018 Symposia on VLSI Technology and Circuits

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ER -

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW

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