• Ming Ding
  • Zhihao Zhou
  • Yao-Hong Liu
  • Stefano Traferro
  • Christian Bachmann
  • Kathleen Philips
  • Fabio Sebastiano
A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of ΣΔ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <;20 ppm) and temperature stability (106 ppm/°C).
Original languageEnglish
Pages (from-to)30-33
Number of pages4
JournalIEEE Solid State Circuits Letters
Issue number2
Publication statusPublished - Feb 2018

    Research areas

  • Digital-intensive, frequency locked-loop, Internet of Things (IoT), low-power, oscillator, wakeup timer

ID: 47856411