Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.

Original languageEnglish
Title of host publication2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
Subtitle of host publicationDigest of technical papers
EditorsL.J. Fujino
Place of PublicationPiscataway, NJ
Number of pages3
ISBN (Electronic)978-1-5090-4940-0
ISBN (Print)978-1-5386-2227-8
Publication statusPublished - 2018
Event65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
Duration: 11 Feb 201815 Feb 2018


Conference65th IEEE International Solid-State Circuits Conference, ISSCC 2018
CountryUnited States
CitySan Francisco

    Research areas

  • Robustness, Modulation, Clocks, Signal to noise ratio, Linearity, Dynamic range

ID: 47147056