A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Peng Chen; Feifei Zhang; Zhirui Zong; Suoping Hu; Teerachot Siriburanon; Robert Bogdan Staszewski

doi:10.1109/JSSC.2019.2939663

A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Peng Chen^*, Feifei Zhang, Zhirui Zong, Suoping Hu, Teerachot Siriburanon, Robert Bogdan Staszewski

^*Corresponding author for this work

Electronics

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Abstract

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

Original language	English
Article number	8850049
Pages (from-to)	3075-3085
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2019.2939663
Publication status	Published - 1 Nov 2019

Keywords

Capacitor-based digital-to-analog converter (C-DAC)
constant slope
digital-to-time converter (DTC)
femtosecond resolution
integral nonlinearity (INL)
phase-locked loop (PLL)
power-efficient
ultra-low power (ULP)

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10.1109/JSSC.2019.2939663

08850049Final published version, 4.13 MBLicence: CC BY

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title = "A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS",

abstract = "This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.",

keywords = "Capacitor-based digital-to-analog converter (C-DAC), constant slope, digital-to-time converter (DTC), femtosecond resolution, integral nonlinearity (INL), phase-locked loop (PLL), power-efficient, ultra-low power (ULP)",

author = "Peng Chen and Feifei Zhang and Zhirui Zong and Suoping Hu and Teerachot Siriburanon and Staszewski, {Robert Bogdan}",

year = "2019",

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doi = "10.1109/JSSC.2019.2939663",

language = "English",

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AU - Chen, Peng

AU - Zhang, Feifei

AU - Zong, Zhirui

AU - Hu, Suoping

AU - Siriburanon, Teerachot

AU - Staszewski, Robert Bogdan

PY - 2019/11/1

Y1 - 2019/11/1

N2 - This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

AB - This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.

KW - Capacitor-based digital-to-analog converter (C-DAC)

KW - constant slope

KW - digital-to-time converter (DTC)

KW - femtosecond resolution

KW - integral nonlinearity (INL)

KW - phase-locked loop (PLL)

KW - power-efficient

KW - ultra-low power (ULP)

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

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M1 - 8850049

ER -

A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

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Keywords

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