Abstract
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.
Original language | English |
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Article number | 8850049 |
Pages (from-to) | 3075-3085 |
Number of pages | 11 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 54 |
Issue number | 11 |
DOIs | |
Publication status | Published - 1 Nov 2019 |
Keywords
- Capacitor-based digital-to-analog converter (C-DAC)
- constant slope
- digital-to-time converter (DTC)
- femtosecond resolution
- integral nonlinearity (INL)
- phase-locked loop (PLL)
- power-efficient
- ultra-low power (ULP)