TY - JOUR
T1 - A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
AU - Jiang, Hui
AU - Ligouras, Costantino
AU - Nihtianov, Stoyan
AU - Makinwa, Kofi
N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
PY - 2018
Y1 - 2018
N2 - When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.
AB - When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.
KW - Chopping
KW - quantization noise fold-back
KW - energyefficient
KW - capacitively-coupled instrumentation amplifier
KW - continuous-time delta-sigma modulator
KW - Wheatstone bridge sensor
KW - readout
U2 - 10.1109/LSSC.2018.2803447
DO - 10.1109/LSSC.2018.2803447
M3 - Article
VL - 1
SP - 18
EP - 21
JO - IEEE Solid State Circuits Letters
JF - IEEE Solid State Circuits Letters
IS - 1
ER -