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A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme. / Jiang, Hui; Ligouras, Costantino; Nihtianov, Stoyan; Makinwa, Kofi.

In: IEEE Solid State Circuits Letters, Vol. 1, No. 1, 2018, p. 18-21.

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@article{d5d8d413fc824eec8613fcce3cb47273,
title = "A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme",
abstract = "When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.",
keywords = "Chopping, quantization noise fold-back, energyefficient, capacitively-coupled instrumentation amplifier, continuous-time delta-sigma modulator, Wheatstone bridge sensor, readout",
author = "Hui Jiang and Costantino Ligouras and Stoyan Nihtianov and Kofi Makinwa",
note = "Accepted Author Manuscript",
year = "2018",
doi = "10.1109/LSSC.2018.2803447",
language = "English",
volume = "1",
pages = "18--21",
journal = "IEEE Solid State Circuits Letters",
issn = "2573-9603",
publisher = "Institute of Electrical and Electronics Engineers",
number = "1",

}

RIS

TY - JOUR

T1 - A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme

AU - Jiang, Hui

AU - Ligouras, Costantino

AU - Nihtianov, Stoyan

AU - Makinwa, Kofi

N1 - Accepted Author Manuscript

PY - 2018

Y1 - 2018

N2 - When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.

AB - When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.

KW - Chopping

KW - quantization noise fold-back

KW - energyefficient

KW - capacitively-coupled instrumentation amplifier

KW - continuous-time delta-sigma modulator

KW - Wheatstone bridge sensor

KW - readout

U2 - 10.1109/LSSC.2018.2803447

DO - 10.1109/LSSC.2018.2803447

M3 - Article

VL - 1

SP - 18

EP - 21

JO - IEEE Solid State Circuits Letters

JF - IEEE Solid State Circuits Letters

SN - 2573-9603

IS - 1

ER -

ID: 46974350