Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, however they are typically discrete bulky devices, thus preventing miniaturization. To address this issue, we propose a fully integrated 40-nm CMOS 6.5-GHz circulator operating from 300 K to 4.2 K. At 300 K, it achieves a 2.2-dB insertion loss, an 18-dB isolation, and a 2.4-dB noise figure over the 1-dB bandwidth from 5.6 GHz to 7.4 GHz, with a core power of only 2.5 mW. This improves to 2.1 mW core power at 4.2 K, while showing 1.3-dB insertion loss and 17-dB isolation over the 1-dB bandwidth from 5.8 GHz to 7.6 GHz. The circuit achieves a record-low core power and a 1.6× wider fractional bandwidth than the state-of-the-art, thus allowing its use for multiple channels in power-constrained cryogenic refrigerators. These advances are enabled by a fully-passive architecture based on LC all-pass filters, allowing the use of a lower clock frequency than in prior art.

Original languageEnglish
Title of host publication2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
PublisherIEEE
Pages107-110
Number of pages4
ISBN (Electronic)978-1-7281-1701-0
ISBN (Print)978-1-7281-1702-7
DOIs
Publication statusPublished - 2019
Event2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019 - Boston, United States
Duration: 2 Jun 20194 Jun 2019

Conference

Conference2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
CountryUnited States
CityBoston
Period2/06/194/06/19

    Research areas

  • circulator, Cryo-CMOS, quantum computing, qubit, qubit readout, spin qubit, superconducting qubit

ID: 57106960