A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

Shakil Akter; Rohan Sehgal; Frank van der Goes; Kofi A.A. Makinwa; Klaas Bult

doi:10.1109/JSSC.2018.2859415

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

Shakil Akter, Rohan Sehgal, Frank van der Goes, Kofi A.A. Makinwa, Klaas Bult

Research output: Contribution to journal › Article › Scientific › peer-review

16 Citations (Scopus)

312 Downloads (Pure)

Abstract

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12,000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8x improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

Original language	English
Pages (from-to)	2939-2950
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	53
Issue number	10
DOIs	https://doi.org/10.1109/JSSC.2018.2859415
Publication status	Published - 2018

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

Analog gain correction
analog-to-digital conversion
Calibration
Capacitance
Capacitors
class-AB residue amplifier
Clocks
differential sampling
incomplete settling
Linearity
Power dissipation
split-ADC calibration
split-capacitor bias control technique.
Transistors

Access to Document

10.1109/JSSC.2018.2859415

A_66-dB_SNDR_Pipelined_Split-ADC_in_40-nm_CMOS_Using_a_Class-AB_Residue_AmplifierFinal published version, 3.87 MB

Cite this

@article{dc60a568f9f14bceb03cd71d1b922612,

title = "A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier",

abstract = "This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12,000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8x improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.",

keywords = "Analog gain correction, analog-to-digital conversion, Calibration, Capacitance, Capacitors, class-AB residue amplifier, Clocks, differential sampling, incomplete settling, Linearity, Power dissipation, split-ADC calibration, split-capacitor bias control technique., Transistors",

author = "Shakil Akter and Rohan Sehgal and {van der Goes}, Frank and Makinwa, {Kofi A.A.} and Klaas Bult",

note = "Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. ",

year = "2018",

doi = "10.1109/JSSC.2018.2859415",

language = "English",

volume = "53",

pages = "2939--2950",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "IEEE",

number = "10",

}

TY - JOUR

T1 - A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

AU - Akter, Shakil

AU - Sehgal, Rohan

AU - van der Goes, Frank

AU - Makinwa, Kofi A.A.

AU - Bult, Klaas

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2018

Y1 - 2018

N2 - This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12,000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8x improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

AB - This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12,000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8x improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.

KW - Analog gain correction

KW - analog-to-digital conversion

KW - Calibration

KW - Capacitance

KW - Capacitors

KW - class-AB residue amplifier

KW - Clocks

KW - differential sampling

KW - incomplete settling

KW - Linearity

KW - Power dissipation

KW - split-ADC calibration

KW - split-capacitor bias control technique.

KW - Transistors

UR - http://www.scopus.com/inward/record.url?scp=85052710982&partnerID=8YFLogxK

UR - http://resolver.tudelft.nl/uuid:dc60a568-f9f1-4bce-b03c-d71d1b922612

U2 - 10.1109/JSSC.2018.2859415

DO - 10.1109/JSSC.2018.2859415

M3 - Article

AN - SCOPUS:85052710982

SN - 0018-9200

VL - 53

SP - 2939

EP - 2950

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 10

ER -

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

Abstract

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this