This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.

Original languageEnglish
Pages (from-to)1115-1126
Number of pages12
JournalIEEE Journal of Solid State Circuits
Issue number4
Publication statusPublished - 2018

    Research areas

  • Amplifier, analog linearization technique, analog-to-digital converter (ADC), capacitive degeneration, cross-coupled capacitors, digital nonlinearity calibration, dynamic residue amplifier, integrator, split-capacitor technique

ID: 42963826