Abstract
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.
Original language | English |
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Pages (from-to) | 1115-1126 |
Number of pages | 12 |
Journal | IEEE Journal of Solid State Circuits |
Volume | 53 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2018 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- Amplifier
- analog linearization technique
- analog-to-digital converter (ADC)
- capacitive degeneration
- cross-coupled capacitors
- digital nonlinearity calibration
- dynamic residue amplifier
- integrator
- split-capacitor technique