This paper presents a proof-of-concept CMOS image sensor (CIS) having a continuous column readout speed of 10 ​MHz. Each column readout chain, from the pixel output to the chip digital outputs, is composed of two cascade programmable gain amplifiers (PGAs) and a 10 bit 1.5 bit/stage pipelined ADC, all operating at 10 ​M samples per second. A digital background calibration method is proposed to remove the nonlinearity resulted from the capacitor mismatches in the multiplying DACs (MDACs) in each pipelined ADC stage. Measurement results from 16 columns of 10 bit single-ended pipelined ADCs show Integral Nonlinearity (INL) around 4 LSB and an Effective Number Of Bits (ENOB) of 8 (reference voltage of 1 Vpp), after being digitally calibrated. Compared to the state-of-the-art column ADCs for high speed CISs, this design has a higher speed with a figure-of-merit (FOM) of 3.2 pJ/conv. The proposed CIS's measured photoelectron transfer characteristics is shown at a column readout rate of 10 ​MHz.

Original languageEnglish
Article number104758
Pages (from-to)1-7
Number of pages7
JournalMicroelectronics Journal
Volume99
DOIs
Publication statusPublished - 2020

    Research areas

  • CMOS image Sensor, Digital background calibration, Digital error correction, High continuous readout speed, Pipelined ADC

ID: 71648874