A CMOS image sensor with a column-level multiple-ramp single-slope ADC

MF Snoeij; P Donegan; AJP Theuwissen; KAA Makinwa; JH Huijsing

doi:10.1109/ISSCC.2007.373516

A CMOS image sensor with a column-level multiple-ramp single-slope ADC

MF Snoeij, P Donegan, AJP Theuwissen, KAA Makinwa, JH Huijsing

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

37 Citations (Scopus)

Abstract

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.

Original language	Undefined/Unknown
Title of host publication	Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Editors	s.n.
Place of Publication	San Francisco, USA
Publisher	IEEE Society
Pages	1-4
Number of pages	4
ISBN (Print)	1-4244-0853-9
DOIs	https://doi.org/10.1109/ISSCC.2007.373516
Publication status	Published - 2007
Event	IEEE International solid-state circuits conference, 2007, San Francisco - San Francisco, USA Duration: 11 Feb 2007 → 15 Feb 2007

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE International solid-state circuits conference, 2007, San Francisco
Period	11/02/07 → 15/02/07

Access to Document

10.1109/ISSCC.2007.373516

Cite this

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title = "A CMOS image sensor with a column-level multiple-ramp single-slope ADC",

abstract = "A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.",

author = "MF Snoeij and P Donegan and AJP Theuwissen and KAA Makinwa and JH Huijsing",

year = "2007",

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language = "Undefined/Unknown",

isbn = "1-4244-0853-9",

publisher = "IEEE Society",

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booktitle = "Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International",

note = "IEEE International solid-state circuits conference, 2007, San Francisco ; Conference date: 11-02-2007 Through 15-02-2007",

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Snoeij, MF, Donegan, P, Theuwissen, AJP , Makinwa, KAA & Huijsing, JH 2007, A CMOS image sensor with a column-level multiple-ramp single-slope ADC. in s.n. (ed.), Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International. IEEE Society, San Francisco, USA, pp. 1-4, IEEE International solid-state circuits conference, 2007, San Francisco, 11/02/07. https://doi.org/10.1109/ISSCC.2007.373516

A CMOS image sensor with a column-level multiple-ramp single-slope ADC. / Snoeij, MF; Donegan, P; Theuwissen, AJP et al.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International. ed. / s.n. San Francisco, USA: IEEE Society, 2007. p. 1-4.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

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AU - Huijsing, JH

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AB - A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.

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