Abstract
This paper presents a front-end application-specific integrated circuit (ASIC) that demonstrates the feasibility of inprobe digitization for next-generation miniature 3-D ultrasound probes with acceptable power- and area-efficiency. The proposed design employs a low-power charge-domain ADC that is directly merged with the sample-and-hold delay lines in each subarray, and high-speed datalinks at the ASIC periphery to realize an additional channel-count reduction compared to prior work based on analog subarray beamforming. The 4.8 × 2 mm2 ASIC, which has a compact layout element-matched to a 5-MHz 150-μm-pitch PZT matrix transducer, achieves an overall 36-fold channel-count reduction and a state-of-the-art power-efficiency with less than 1 mW/element power dissipation while receiving, which is acceptable even when scaled up to a 1000-element probe. The prototype ASIC has been fabricated in a 0.18 μm CMOS process. Its functionality has been successfully evaluated with both electrical and acoustical measurements.
Original language | English |
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Title of host publication | 2017 IEEE International Ultrasonics Symposium (IUS) |
Publisher | IEEE |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-5386-3383-0 |
DOIs | |
Publication status | Published - 2017 |
Event | 2017 IEEE International Ultrasonics Symposium - Washington, DC, United States Duration: 6 Sept 2017 → 9 Sept 2017 http://ewh.ieee.org/conf/ius/2017/ |
Conference
Conference | 2017 IEEE International Ultrasonics Symposium |
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Abbreviated title | IUS 2017 |
Country/Territory | United States |
City | Washington, DC |
Period | 6/09/17 → 9/09/17 |
Internet address |
Keywords
- 2-D PZT matrix
- Frond-End ASIC
- In-probe Digitization
- Low-power ADC
- Miniature 3-D Ultrasound probe
- Subarray Beamforming