This paper presents a front-end application-specific integrated circuit (ASIC) that demonstrates the feasibility of inprobe digitization for next-generation miniature 3-D ultrasound probes with acceptable power- and area-efficiency. The proposed design employs a low-power charge-domain ADC that is directly merged with the sample-and-hold delay lines in each subarray, and high-speed datalinks at the ASIC periphery to realize an additional channel-count reduction compared to prior work based on analog subarray beamforming. The 4.8 × 2 mm2 ASIC, which has a compact layout element-matched to a 5-MHz 150-μm-pitch PZT matrix transducer, achieves an overall 36-fold channel-count reduction and a state-of-the-art power-efficiency with less than 1 mW/element power dissipation while receiving, which is acceptable even when scaled up to a 1000-element probe. The prototype ASIC has been fabricated in a 0.18 μm CMOS process. Its functionality has been successfully evaluated with both electrical and acoustical measurements.

Original languageEnglish
Title of host publication2017 IEEE International Ultrasonics Symposium (IUS)
PublisherIEEE
Pages1-4
Number of pages4
ISBN (Electronic)978-1-5386-3383-0
DOIs
Publication statusPublished - 2017
Event2017 IEEE International Ultrasonics Symposium - Washington, DC, United States
Duration: 6 Sep 20179 Sep 2017
http://ewh.ieee.org/conf/ius/2017/

Conference

Conference2017 IEEE International Ultrasonics Symposium
Abbreviated titleIUS 2017
CountryUnited States
CityWashington, DC
Period6/09/179/09/17
Internet address

    Research areas

  • 2-D PZT matrix, Frond-End ASIC, In-probe Digitization, Low-power ADC, Miniature 3-D Ultrasound probe, Subarray Beamforming

ID: 37140806