A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

M. Babaie; F Kuo; H. N. R. Chen; L Cho; C. P. Jou; F. L. Hsueh; M. Shahmohammadi; R. B. Staszewski

doi:10.1109/JSSC.2016.2551738

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

M. Babaie, F Kuo, H. N. R. Chen, L Cho, C. P. Jou, F. L. Hsueh, M. Shahmohammadi, R. B. Staszewski

Electronics

Research output: Contribution to journal › Article › Scientific › peer-review

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Abstract

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

Original language	English
Pages (from-to)	1547-1565
Number of pages	19
Journal	IEEE Journal of Solid State Circuits
Volume	51
Issue number	7
DOIs	https://doi.org/10.1109/JSSC.2016.2551738
Publication status	Published - 2016

Keywords

Bluetooth
CMOS digital integrated circuits
MOSFET circuits
constant current sources
digital phase locked loops
low-power electronics
oscillators
radio transmitters
radiofrequency integrated circuits
radiofrequency power amplifiers
1/f noise reduction
Bluetooth low-energy mode
CMOS transistors
all-digital PLL
class-E-F2 switching power amplifier
digitally controlled oscillator
direct DCO data modulation
efficiency 36 percent
energy-hungry RF circuits
fully integrated Bluetooth low-energy transmitter architecture
metal density
power 3.6 mW
power 5.5 mW
sampling rate reduction
size 28 nm
supply voltage reduction
switching current sources
threshold voltage
ultra-low power radios
CMOS integrated circuits
Inductors
Oscillators
Q-factor
Radio frequency
Radio transmitters
Switches
All-digital PLL
Bluetooth Low-Energy
Internet of Things (IoT)
class-E/F 2 power amplifier
low-power transmitter
low-voltage oscillator
switching current-source oscillator

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10.1109/JSSC.2016.2551738

07476842Final published version, 8.64 MB

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title = "A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm",

abstract = "We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.",

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author = "M. Babaie and F Kuo and Chen, {H. N. R.} and L Cho and Jou, {C. P.} and Hsueh, {F. L.} and M. Shahmohammadi and Staszewski, {R. B.}",

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language = "English",

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AU - Chen, H. N. R.

AU - Cho, L

AU - Jou, C. P.

AU - Hsueh, F. L.

AU - Shahmohammadi, M.

AU - Staszewski, R. B.

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AB - We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

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KW - radiofrequency power amplifiers

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JO - IEEE Journal of Solid State Circuits

JF - IEEE Journal of Solid State Circuits

IS - 7

ER -

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

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