This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.
Original languageEnglish
Title of host publication2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Place of PublicationDanvers, MA
PublisherIEEE
Pages196 - 199
Number of pages4
ISBN (Electronic)978-1-5090-4626-3
DOIs
Publication statusPublished - 2017
EventRFIC 2017: IEEE Radio Frequency Integrated Circuits Symposium - Hawaii Convention Center, Honolulu, HI, United States
Duration: 4 Jun 20176 Jun 2017
http://rfic-ieee.org/

Conference

ConferenceRFIC 2017
CountryUnited States
CityHonolulu, HI
Period4/06/176/06/17
Internet address

    Research areas

  • Doherty transmitter, digital-intensive polar, efficiency enhancement, DPD, phase modulator, on-chip combiner

ID: 37688728