A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; Kofi A.A. Makinwa

doi:10.1109/JSSC.2016.2637003

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A.A. Makinwa

Microelectronics

Research output: Contribution to journal › Article › Scientific › peer-review

14 Citations (Scopus)

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Abstract

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to V_DD, while its 4-kB ROM and the 16-kB SRAM are powered from V_DD to 2 V_DD. Since the memory and logic will, in general, draw different supply currents, the midrail V_DD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and V_DD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.

Original language	English
Article number	7815353
Pages (from-to)	950-960
Number of pages	11
Journal	IEEE Journal of Solid State Circuits
Volume	52
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2016.2637003
Publication status	Published - 2017

Bibliographical note

Accepted Author Manuscript

Keywords

Balanced voltage islands
charge recycling
level shifter
microcontrollers
power management
switched capacitor regulators
voltage stacking

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10.1109/JSSC.2016.2637003

30247109 - JSSC2637003Accepted author manuscript, 1.22 MB

Cite this

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title = "A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling",

abstract = "A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.",

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author = "Kristof Blutman and Ajay Kapoor and Arjun Majumdar and Martinez, {Jacinto Garcia} and Juan Echeverri and Leo Sevat and {van der Wel}, {Arnoud P.} and Hamed Fatemi and Makinwa, {Kofi A.A.}",

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AU - Echeverri, Juan

AU - Sevat, Leo

AU - van der Wel, Arnoud P.

AU - Fatemi, Hamed

AU - Makinwa, Kofi A.A.

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AB - A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.

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A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

Abstract

Bibliographical note

Keywords

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