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  • a1-chen

    Final published version, 763 KB, PDF-document

DOI

In this paper, we present the design in reconfigurable logic of a matrix multiplier for matrices of 32-bit posit numbers with es=2 [1]. Vector dot products are computed without intermediate rounding as suggested by the proposed posit standard to maximally retain precision. An initial implementation targets the CAPI 1.0 interface on the POWER8 processor and achieves about 10Gpops (Giga posit operations per second). Follow-on implementations targeting CAPI 2.0 and OpenCAPI 3.0 on POWER9 are expected to achieve up to 64Gpops. Our design is available under a permissive open source license at https://github.com/ChenJianyunp/Unum_matrix_multiplier. We hope the current work, which works on CAPI 1.0, along with future community contributions, will help enable a more extensive exploration of this proposed new format.

Original languageEnglish
Title of host publicationProceedings of the Conference for Next Generation Arithmetic, CoNGA 2018
PublisherAssociation for Computing Machinery (ACM)
Pages1-5
Number of pages5
ISBN (Electronic)978-1-4503-6414-0
DOIs
Publication statusPublished - 2018
EventCoNGA 2018: The Conference for Next Generation Arithmetic - Singapore, Singapore
Duration: 28 Mar 201828 Mar 2018

Conference

ConferenceCoNGA 2018
CountrySingapore
CitySingapore
Period28/03/1828/03/18

    Research areas

  • Dot-product, Matrix-multiplier, Posit number, OA-Fund TU Delft

ID: 45596799