• Kristof Blutman
  • A. Kapoor
  • Arjun Majumdar
  • J.G. Martinez
  • J. Echeverri
  • L. Sevat
  • A. van der Wel
  • H. Fatemi
  • J.P. de Gyvez
  • K.A.A. Makinwa
This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS).
Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Circuits, VLSI-Circuits 2016
Subtitle of host publicationDigest of Technical Papers
Place of PublicationPiscataway, NJ
Number of pages2
ISBN (Electronic)978-1-5090-0635-9
Publication statusPublished - 22 Sep 2016
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: 14 Jun 201617 Jun 2016


Conference30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
CountryUnited States

    Research areas

  • Power capacitors, Stacking, Read only memory, Random access memory, Voltage control, Clocks, Current measurement

ID: 11340718