A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

TM Thomas; JY Hur; K Bertels; GN Gaydadjiev

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

TM Thomas, JY Hur, K Bertels, GN Gaydadjiev

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	2010 IEEE 8th symp. on application specific processors
Editors	s.n.
Place of Publication	CA, USA
Publisher	IEEE Society
Pages	105-110
Number of pages	6
ISBN (Print)	978-1-4244-7952-8
Publication status	Published - 2010
Event	SASP 2010 - CA, USA Duration: 13 Jun 2010 → 14 Jun 2010

Publication series

Name
Publisher	IEEE

Conference

Conference	SASP 2010
Period	13/06/10 → 14/06/10

Keywords

conference contrib. refereed
Conf.proc. > 3 pag

Cite this

@inproceedings{dbe2d598aea947958de0f9fffc0ae719,

title = "A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices",

keywords = "conference contrib. refereed, Conf.proc. > 3 pag",

author = "TM Thomas and JY Hur and K Bertels and GN Gaydadjiev",

year = "2010",

language = "Undefined/Unknown",

isbn = "978-1-4244-7952-8",

publisher = "IEEE Society",

pages = "105--110",

editor = "s.n.",

booktitle = "2010 IEEE 8th symp. on application specific processors",

note = "SASP 2010 ; Conference date: 13-06-2010 Through 14-06-2010",

}

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. / Thomas, TM; Hur, JY; Bertels, K et al.
2010 IEEE 8th symp. on application specific processors. ed. / s.n. CA, USA: IEEE Society, 2010. p. 105-110.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

AU - Thomas, TM

AU - Hur, JY

AU - Bertels, K

AU - Gaydadjiev, GN

PY - 2010

Y1 - 2010

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 978-1-4244-7952-8

SP - 105

EP - 110

BT - 2010 IEEE 8th symp. on application specific processors

A2 - s.n., null

PB - IEEE Society

CY - CA, USA

T2 - SASP 2010

Y2 - 13 June 2010 through 14 June 2010

ER -