Standard

A sampling problem from lithography for chip layout. / Cator, EA; Dijkema, TJ; Hochstenbach, M; Mulckhuyse, W; Peletier, MA; Prokert, G; Weij, W; Worm, D.

Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry. ed. / RH Bisseling; K Dajani; TJ Dijkema; J van de Leur; PA Zegeling. Amsterdam : Centrum Wiskunde & Informatica, 2007. p. 45-53.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

Harvard

Cator, EA, Dijkema, TJ, Hochstenbach, M, Mulckhuyse, W, Peletier, MA, Prokert, G, Weij, W & Worm, D 2007, A sampling problem from lithography for chip layout. in RH Bisseling, K Dajani, TJ Dijkema, J van de Leur & PA Zegeling (eds), Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry. Centrum Wiskunde & Informatica, Amsterdam, pp. 45-53, ESGI58/SWI2007, 29/01/07.

APA

Cator, EA., Dijkema, TJ., Hochstenbach, M., Mulckhuyse, W., Peletier, MA., Prokert, G., ... Worm, D. (2007). A sampling problem from lithography for chip layout. In RH. Bisseling, K. Dajani, TJ. Dijkema, J. van de Leur, & PA. Zegeling (Eds.), Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry (pp. 45-53). Amsterdam: Centrum Wiskunde & Informatica.

Vancouver

Cator EA, Dijkema TJ, Hochstenbach M, Mulckhuyse W, Peletier MA, Prokert G et al. A sampling problem from lithography for chip layout. In Bisseling RH, Dajani K, Dijkema TJ, van de Leur J, Zegeling PA, editors, Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry. Amsterdam: Centrum Wiskunde & Informatica. 2007. p. 45-53

Author

Cator, EA ; Dijkema, TJ ; Hochstenbach, M ; Mulckhuyse, W ; Peletier, MA ; Prokert, G ; Weij, W ; Worm, D. / A sampling problem from lithography for chip layout. Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry. editor / RH Bisseling ; K Dajani ; TJ Dijkema ; J van de Leur ; PA Zegeling. Amsterdam : Centrum Wiskunde & Informatica, 2007. pp. 45-53

BibTeX

@inproceedings{1aeadf68fd6c48ba95f2fcb78f20d846,
title = "A sampling problem from lithography for chip layout",
keywords = "Wiskunde en Informatica, Techniek, technische Wiskunde en Informatica, Conf.proc. > 3 pag",
author = "EA Cator and TJ Dijkema and M Hochstenbach and W Mulckhuyse and MA Peletier and G Prokert and W Weij and D Worm",
note = "NEO",
year = "2007",
language = "Undefined/Unknown",
publisher = "Centrum Wiskunde & Informatica",
pages = "45--53",
editor = "RH Bisseling and K Dajani and TJ Dijkema and {van de Leur}, J and PA Zegeling",
booktitle = "Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry",

}

RIS

TY - GEN

T1 - A sampling problem from lithography for chip layout

AU - Cator, EA

AU - Dijkema, TJ

AU - Hochstenbach, M

AU - Mulckhuyse, W

AU - Peletier, MA

AU - Prokert, G

AU - Weij, W

AU - Worm, D

N1 - NEO

PY - 2007

Y1 - 2007

KW - Wiskunde en Informatica

KW - Techniek

KW - technische Wiskunde en Informatica

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SP - 45

EP - 53

BT - Proceedings of the Fifty-Eighth European Study Group Mathematics with Industry

A2 - Bisseling, RH

A2 - Dajani, K

A2 - Dijkema, TJ

A2 - van de Leur, J

A2 - Zegeling, PA

PB - Centrum Wiskunde & Informatica

CY - Amsterdam

ER -

ID: 2682137