A Security Verification Template to Assess Cache Architecture Vulnerabilities

Tara Ghasempouri; Jaan Raik; Kolin Paul; Cezar Reinbrecht; Said Hamdioui; Mottaqiallah Taouil

doi:10.1109/DDECS50862.2020.9095707

A Security Verification Template to Assess Cache Architecture Vulnerabilities

Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

99 Downloads (Pure)

Abstract

In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.

Original language	English
Title of host publication	2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Subtitle of host publication	Proceedings
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-7281-9938-2
ISBN (Print)	978-1-7281-9939-9
DOIs	https://doi.org/10.1109/DDECS50862.2020.9095707
Publication status	Published - 2020
Event	23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 - Novi Sad, Serbia Duration: 22 Apr 2020 → 24 Apr 2020

Conference

Conference	23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020
Country/Territory	Serbia
City	Novi Sad
Period	22/04/20 → 24/04/20

Bibliographical note

Accepted author manuscript

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10.1109/DDECS50862.2020.9095707

DDECS_2020___Formal_Security_Verification_of_Caches___TUT_TUDAccepted author manuscript, 405 KB

Cite this

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title = "A Security Verification Template to Assess Cache Architecture Vulnerabilities",

abstract = "In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.",

author = "Tara Ghasempouri and Jaan Raik and Kolin Paul and Cezar Reinbrecht and Said Hamdioui and Mottaqiallah Taouil",

note = "Accepted author manuscript; 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 ; Conference date: 22-04-2020 Through 24-04-2020",

year = "2020",

doi = "10.1109/DDECS50862.2020.9095707",

language = "English",

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Ghasempouri, T, Raik, J, Paul, K, Reinbrecht, C, Hamdioui, S & Taouil, M 2020, A Security Verification Template to Assess Cache Architecture Vulnerabilities. in 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): Proceedings., 9095707, IEEE, pp. 1-6, 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020, Novi Sad, Serbia, 22/04/20. https://doi.org/10.1109/DDECS50862.2020.9095707

A Security Verification Template to Assess Cache Architecture Vulnerabilities. / Ghasempouri, Tara; Raik, Jaan; Paul, Kolin et al.
2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): Proceedings. IEEE, 2020. p. 1-6 9095707.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - A Security Verification Template to Assess Cache Architecture Vulnerabilities

AU - Ghasempouri, Tara

AU - Raik, Jaan

AU - Paul, Kolin

AU - Reinbrecht, Cezar

AU - Hamdioui, Said

AU - Taouil, Mottaqiallah

N1 - Accepted author manuscript

PY - 2020

Y1 - 2020

N2 - In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.

AB - In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.

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SP - 1

EP - 6

BT - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

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T2 - 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020

Y2 - 22 April 2020 through 24 April 2020

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A Security Verification Template to Assess Cache Architecture Vulnerabilities

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