Documents

  • 1912.06461

    Accepted author manuscript, 858 KB, PDF document

DOI

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

Original languageEnglish
Title of host publication2019 IEEE International Electron Devices Meeting, IEDM 2019
EditorsMariko Takayanagi
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages4
Volume2019-December
ISBN (Electronic)9781728140315
DOIs
Publication statusPublished - 2019
Event65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
Duration: 7 Dec 201911 Dec 2019

Conference

Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
CountryUnited States
CitySan Francisco
Period7/12/1911/12/19

ID: 72218989