With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to
size, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI
circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The
experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.

Original languageEnglish
Title of host publication2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
EditorsW. Zhao, C.A. Moritz
Place of PublicationNew York
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
ISBN (Electronic)978-1-4503-4330-5
ISBN (Print)978-1-4673-8927-3
Publication statusPublished - 2016
Event2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China
Duration: 18 Jul 201620 Jul 2016


Conference2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated titleNANOARCH 2016

    Research areas

  • Statistical Timing Analysis, Delay Estimation, Delay PDF Propagation, Reliability, VLSI

ID: 10409782