Abstract
With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to
size, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI
circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The
experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.
Original language | English |
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Title of host publication | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
Editors | W. Zhao, C.A. Moritz |
Place of Publication | New York |
Publisher | Association for Computing Machinery (ACM) |
Pages | 79-84 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-4503-4330-5 |
ISBN (Print) | 978-1-4673-8927-3 |
DOIs | |
Publication status | Published - 2016 |
Event | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016 |
Conference
Conference | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
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Abbreviated title | NANOARCH 2016 |
Country/Territory | China |
City | Beijing |
Period | 18/07/16 → 20/07/16 |
Keywords
- Statistical Timing Analysis
- Delay Estimation
- Delay PDF Propagation
- Reliability
- VLSI