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A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors. / Romijn, Joost; Vollebregt, Sten; van Zeijl, Henk W.; Sarro, Pasqualina M.

2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). Piscataway : IEEE, 2019. p. 260-263 8870741.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Romijn, J, Vollebregt, S, van Zeijl, HW & Sarro, PM 2019, A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors. in 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS)., 8870741, IEEE, Piscataway, pp. 260-263, 32nd IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2019, Seoul, Korea, Republic of, 27/01/19. https://doi.org/10.1109/MEMSYS.2019.8870741

APA

Vancouver

Romijn J, Vollebregt S, van Zeijl HW, Sarro PM. A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors. In 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). Piscataway: IEEE. 2019. p. 260-263. 8870741 https://doi.org/10.1109/MEMSYS.2019.8870741

Author

Romijn, Joost ; Vollebregt, Sten ; van Zeijl, Henk W. ; Sarro, Pasqualina M. / A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors. 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS). Piscataway : IEEE, 2019. pp. 260-263

BibTeX

@inproceedings{76a67f187d39435ebeaccc35ceebeb6b,
title = "A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors",
abstract = "In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.",
author = "Joost Romijn and Sten Vollebregt and {van Zeijl}, {Henk W.} and Sarro, {Pasqualina M.}",
note = "Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.",
year = "2019",
doi = "10.1109/MEMSYS.2019.8870741",
language = "English",
isbn = "978-1-7281-1611-2",
pages = "260--263",
booktitle = "2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors

AU - Romijn, Joost

AU - Vollebregt, Sten

AU - van Zeijl, Henk W.

AU - Sarro, Pasqualina M.

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2019

Y1 - 2019

N2 - In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.

AB - In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.

UR - http://www.scopus.com/inward/record.url?scp=85074332842&partnerID=8YFLogxK

U2 - 10.1109/MEMSYS.2019.8870741

DO - 10.1109/MEMSYS.2019.8870741

M3 - Conference contribution

SN - 978-1-7281-1611-2

SP - 260

EP - 263

BT - 2019 IEEE 32nd International Conference on Micro Electro Mechanical Systems (MEMS)

PB - IEEE

CY - Piscataway

ER -

ID: 66538204