Documents

  • a5-van_Dam

    Final published version, 4 MB, PDF-document

DOI

The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.
Original languageEnglish
Title of host publicationCoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019
Place of PublicationNew York, NY
PublisherAssociation for Computing Machinery (ACM)
Pages5:1--5:10
Number of pages10
ISBN (Print)978-1-4503-7139-1
DOIs
Publication statusPublished - 2019
EventCoNGA 2019 : The Conference for Next Generation Arithmetic - Singapore, Singapore
Duration: 13 Mar 201914 Mar 2019

Conference

ConferenceCoNGA 2019
Abbreviated titleCoNGA'19
CountrySingapore
CitySingapore
Period13/03/1914/03/19

    Research areas

  • Accelerator, Arithmetic, BLAS, Decimal accuracy, FPGA, Pair-HMM, Posit, Unum, Unum-III, OA-Fund TU Delft

ID: 53163693