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An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM. / van Dam, Laurens ; Peltenburg, Johan; Al-Ars, Zaid; Hofstee, H. Peter.

CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019. New York, NY : Association for Computing Machinery (ACM), 2019. p. 5:1--5:10 5.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

van Dam, L, Peltenburg, J, Al-Ars, Z & Hofstee, HP 2019, An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM. in CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019., 5, Association for Computing Machinery (ACM), New York, NY, pp. 5:1--5:10, CoNGA 2019 , Singapore, Singapore, 13/03/19. https://doi.org/10.1145/3316279.3316284

APA

van Dam, L., Peltenburg, J., Al-Ars, Z., & Hofstee, H. P. (2019). An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM. In CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019 (pp. 5:1--5:10). [5] New York, NY: Association for Computing Machinery (ACM). https://doi.org/10.1145/3316279.3316284

Vancouver

van Dam L, Peltenburg J, Al-Ars Z, Hofstee HP. An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM. In CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019. New York, NY: Association for Computing Machinery (ACM). 2019. p. 5:1--5:10. 5 https://doi.org/10.1145/3316279.3316284

Author

van Dam, Laurens ; Peltenburg, Johan ; Al-Ars, Zaid ; Hofstee, H. Peter. / An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM. CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019. New York, NY : Association for Computing Machinery (ACM), 2019. pp. 5:1--5:10

BibTeX

@inproceedings{3e471b6f7c2548cbb906292eab28e8ff,
title = "An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM",
abstract = "The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.",
keywords = "Accelerator, Arithmetic, BLAS, Decimal accuracy, FPGA, Pair-HMM, Posit, Unum, Unum-III, OA-Fund TU Delft",
author = "{van Dam}, Laurens and Johan Peltenburg and Zaid Al-Ars and Hofstee, {H. Peter}",
year = "2019",
doi = "10.1145/3316279.3316284",
language = "English",
isbn = "978-1-4503-7139-1",
pages = "5:1----5:10",
booktitle = "CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019",
publisher = "Association for Computing Machinery (ACM)",
address = "United States",

}

RIS

TY - GEN

T1 - An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM

AU - van Dam, Laurens

AU - Peltenburg, Johan

AU - Al-Ars, Zaid

AU - Hofstee, H. Peter

PY - 2019

Y1 - 2019

N2 - The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.

AB - The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.

KW - Accelerator

KW - Arithmetic

KW - BLAS

KW - Decimal accuracy

KW - FPGA

KW - Pair-HMM

KW - Posit

KW - Unum

KW - Unum-III

KW - OA-Fund TU Delft

UR - http://www.scopus.com/inward/record.url?scp=85065926532&partnerID=8YFLogxK

U2 - 10.1145/3316279.3316284

DO - 10.1145/3316279.3316284

M3 - Conference contribution

SN - 978-1-4503-7139-1

SP - 5:1--5:10

BT - CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019

PB - Association for Computing Machinery (ACM)

CY - New York, NY

ER -

ID: 53163693