An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

Feng-Wei Kuo, Masoud Babaie, Huan-Neng (Ron) Chen, Lan-Chou Cho, Chewn-Pu Jou, Mark Chen, Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

15 Citations (Scopus)
554 Downloads (Pure)

Abstract

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <-107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits -157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <-91 dBc, while fractional spurs are <-55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm$^2$.
Original languageEnglish
Pages (from-to)3756-3768
Number of pages13
JournalIEEE Transactions on Circuits and Systems Part 1: Regular Papers
Volume65
Issue number11
DOIs
Publication statusPublished - 2018

Keywords

  • 4G cellular
  • All-digital PLL (ADPLL)
  • digitally controlled oscillator (DCO)
  • long-term evolution (LTE)
  • spurs
  • time-to-digital converter (TDC)

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