Abstract
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.
Original language | English |
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Title of host publication | Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2018 |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 1-5 |
Number of pages | 5 |
ISBN (Electronic) | 978-1-5386-4881-0 |
DOIs | |
Publication status | Published - May 2018 |
Event | ISCAS 2018: IEEE International Symposium on Circuits and Systems - Florence, Italy Duration: 27 May 2018 → 30 May 2018 http://www.iscas2018.org |
Conference
Conference | ISCAS 2018 |
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Abbreviated title | ISCAS 2018 |
Country/Territory | Italy |
City | Florence |
Period | 27/05/18 → 30/05/18 |
Internet address |
Bibliographical note
Accepted author manuscriptKeywords
- asynchronous
- time-to-digital converter
- TDC
- pipelined
- absolute value based conversion
- time subtraction
- completion detection