In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%
Original languageEnglish
Title of host publicationProceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Subtitle of host publicationProceedings
PublisherIEEE
Pages999-1000
Number of pages2
ISBN (Electronic)978-3-9819263-0-9
DOIs
Publication statusPublished - 2018
EventDesign, Automation and Test in Europe: DATE 2018 - Dresden, Germany
Duration: 19 Mar 201823 Mar 2018

Conference

ConferenceDesign, Automation and Test in Europe
CountryGermany
CityDresden
Period19/03/1823/03/18

    Research areas

  • Delays, Benchmark testing, Production, Monitoring, Libraries, Performance Evaluation

ID: 45542708