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An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns. / Zandrahimi, Mahroo; Debaud, Philippe; Castillejo, Armand; Al-Ars, Zaid.

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, 2018. p. 999-1000.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Zandrahimi, M, Debaud, P, Castillejo, A & Al-Ars, Z 2018, An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns. in Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, pp. 999-1000, Design, Automation and Test in Europe, Dresden, Germany, 19/03/18. https://doi.org/10.23919/DATE.2018.8342155

APA

Zandrahimi, M., Debaud, P., Castillejo, A., & Al-Ars, Z. (2018). An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns. In Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings (pp. 999-1000). IEEE. https://doi.org/10.23919/DATE.2018.8342155

Vancouver

Zandrahimi M, Debaud P, Castillejo A, Al-Ars Z. An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns. In Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE. 2018. p. 999-1000 https://doi.org/10.23919/DATE.2018.8342155

Author

Zandrahimi, Mahroo ; Debaud, Philippe ; Castillejo, Armand ; Al-Ars, Zaid. / An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns. Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, 2018. pp. 999-1000

BibTeX

@inproceedings{ad5492d8a719445f8ce8cd9c57849611,
title = "An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns",
abstract = "In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85{\%}",
keywords = "Delays, Benchmark testing, Production, Monitoring, Libraries, Performance Evaluation",
author = "Mahroo Zandrahimi and Philippe Debaud and Armand Castillejo and Zaid Al-Ars",
year = "2018",
doi = "10.23919/DATE.2018.8342155",
language = "English",
pages = "999--1000",
booktitle = "Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns

AU - Zandrahimi, Mahroo

AU - Debaud, Philippe

AU - Castillejo, Armand

AU - Al-Ars, Zaid

PY - 2018

Y1 - 2018

N2 - In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%

AB - In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%

KW - Delays

KW - Benchmark testing

KW - Production

KW - Monitoring

KW - Libraries

KW - Performance Evaluation

U2 - 10.23919/DATE.2018.8342155

DO - 10.23919/DATE.2018.8342155

M3 - Conference contribution

SP - 999

EP - 1000

BT - Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)

PB - IEEE

ER -

ID: 45542708