To improve charge transfer efficiency (CTE) and eliminate image lag, the impact of spill back effect on image lag is studied in CMOS image sensors (CISs), particularly in high illumination condition. By establishing a mathematical model based on the thermionic emission and drift-diffusion theory, the physical mechanism of spill back effect is described. This model shows that a lower transfer gate (TG) operating voltage and a higher reset voltage of Floating Diffusion (FD) node would mitigate spill back effect. In a 0.18 μ m CMOS process, by setting that the gate voltage of transfer transistor and the reset voltage of FD is 2.8 V and 3.8 V respectively, CTE of the proposed pixel is increased to 100%. The theoretical analysis and TCAD simulation results can explain spill back effect and offer a reference for designing a high CTE pixel in high illumination CISs.

Original languageEnglish
Article number8917594
Pages (from-to)3024-3031
Number of pages8
JournalIEEE Sensors Journal
Volume20
Issue number6
DOIs
Publication statusPublished - 2020

    Research areas

  • charge transfer, CMOS image sensors (CISs), image lag, spill back

ID: 71197067