Standard

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. / Kritchallo, Valery; Braithwaite, Billy; Vermij, Erik; Bertels, Koen; Al-Ars, Zaid.

Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. ed. / F. Hannig; J.M.P. Cardoso; T. Pionteck; D. Fey; W. Schröder-Preikschat; J. Teich. Cham : Springer International Publishing, 2016. p. 251-262 (Lecture Notes in Computer Science; Vol. 9367).

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Kritchallo, V, Braithwaite, B, Vermij, E, Bertels, K & Al-Ars, Z 2016, Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. in F Hannig, JMP Cardoso, T Pionteck, D Fey, W Schröder-Preikschat & J Teich (eds), Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Lecture Notes in Computer Science, vol. 9367, Springer International Publishing, Cham, pp. 251-262, Architecture of Computing Systems, ARCS 2016, Nuremberg, Germany, 4/04/16. https://doi.org/10.1007/978-3-319-30695-7_19

APA

Kritchallo, V., Braithwaite, B., Vermij, E., Bertels, K., & Al-Ars, Z. (2016). Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. In F. Hannig, J. M. P. Cardoso, T. Pionteck, D. Fey, W. Schröder-Preikschat, & J. Teich (Eds.), Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems (pp. 251-262). (Lecture Notes in Computer Science; Vol. 9367). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-30695-7_19

Vancouver

Kritchallo V, Braithwaite B, Vermij E, Bertels K, Al-Ars Z. Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. In Hannig F, Cardoso JMP, Pionteck T, Fey D, Schröder-Preikschat W, Teich J, editors, Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Cham: Springer International Publishing. 2016. p. 251-262. (Lecture Notes in Computer Science). https://doi.org/10.1007/978-3-319-30695-7_19

Author

Kritchallo, Valery ; Braithwaite, Billy ; Vermij, Erik ; Bertels, Koen ; Al-Ars, Zaid. / Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. editor / F. Hannig ; J.M.P. Cardoso ; T. Pionteck ; D. Fey ; W. Schröder-Preikschat ; J. Teich. Cham : Springer International Publishing, 2016. pp. 251-262 (Lecture Notes in Computer Science).

BibTeX

@inproceedings{c19d2b13bf024635aae44c2148157c09,
title = "Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector",
abstract = "We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100{\%} and up to 19x for an accuracy of 99{\%} over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.",
author = "Valery Kritchallo and Billy Braithwaite and Erik Vermij and Koen Bertels and Zaid Al-Ars",
year = "2016",
doi = "10.1007/978-3-319-30695-7_19",
language = "English",
isbn = "978-3-319-30694-0",
series = "Lecture Notes in Computer Science",
publisher = "Springer International Publishing",
pages = "251--262",
editor = "F. Hannig and J.M.P. Cardoso and T. Pionteck and D. Fey and W. Schr{\"o}der-Preikschat and J. Teich",
booktitle = "Architecture of Computing Systems- ARCS 2016",

}

RIS

TY - GEN

T1 - Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

AU - Kritchallo, Valery

AU - Braithwaite, Billy

AU - Vermij, Erik

AU - Bertels, Koen

AU - Al-Ars, Zaid

PY - 2016

Y1 - 2016

N2 - We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.

AB - We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.

U2 - 10.1007/978-3-319-30695-7_19

DO - 10.1007/978-3-319-30695-7_19

M3 - Conference contribution

SN - 978-3-319-30694-0

T3 - Lecture Notes in Computer Science

SP - 251

EP - 262

BT - Architecture of Computing Systems- ARCS 2016

A2 - Hannig, F.

A2 - Cardoso, J.M.P.

A2 - Pionteck, T.

A2 - Fey, D.

A2 - Schröder-Preikschat, W.

A2 - Teich, J.

PB - Springer International Publishing

CY - Cham

ER -

ID: 10682053