Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

Valery Kritchallo; Billy Braithwaite; Erik Vermij; Koen Bertels; Zaid Al-Ars

doi:10.1007/978-3-319-30695-7_19

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

Valery Kritchallo, Billy Braithwaite, Erik Vermij, Koen Bertels, Zaid Al-Ars

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Abstract

We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on three
evaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.

Original language	English
Title of host publication	Architecture of Computing Systems- ARCS 2016
Subtitle of host publication	Proceedings of the 29th International Conference on Architecture of Computing Systems
Editors	F. Hannig, J.M.P. Cardoso, T. Pionteck, D. Fey, W. Schröder-Preikschat, J. Teich
Place of Publication	Cham
Publisher	Springer
Pages	251-262
Number of pages	12
ISBN (Electronic)	978-3-319-30695-7
ISBN (Print)	978-3-319-30694-0
DOIs	https://doi.org/10.1007/978-3-319-30695-7_19
Publication status	Published - 2016
Event	Architecture of Computing Systems, ARCS 2016: 29th International Conference - Nuremberg, Germany Duration: 4 Apr 2016 → 7 Apr 2016

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer International Publishing AG
Volume	9367
ISSN (Electronic)	0302-9743

Conference

Conference	Architecture of Computing Systems, ARCS 2016
Country/Territory	Germany
City	Nuremberg
Period	4/04/16 → 7/04/16

Access to Document

10.1007/978-3-319-30695-7_19

Cite this

Kritchallo, V., Braithwaite, B., Vermij, E., Bertels, K., & Al-Ars, Z. (2016). Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. In F. Hannig, J. M. P. Cardoso, T. Pionteck, D. Fey, W. Schröder-Preikschat, & J. Teich (Eds.), Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems (pp. 251-262). (Lecture Notes in Computer Science; Vol. 9367). Springer. https://doi.org/10.1007/978-3-319-30695-7_19

Kritchallo, Valery ; Braithwaite, Billy ; Vermij, Erik et al. / Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. editor / F. Hannig ; J.M.P. Cardoso ; T. Pionteck ; D. Fey ; W. Schröder-Preikschat ; J. Teich. Cham : Springer, 2016. pp. 251-262 (Lecture Notes in Computer Science).

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title = "Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector",

abstract = "We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.",

author = "Valery Kritchallo and Billy Braithwaite and Erik Vermij and Koen Bertels and Zaid Al-Ars",

year = "2016",

doi = "10.1007/978-3-319-30695-7_19",

language = "English",

isbn = "978-3-319-30694-0",

series = "Lecture Notes in Computer Science",

publisher = "Springer",

pages = "251--262",

editor = "F. Hannig and J.M.P. Cardoso and T. Pionteck and D. Fey and W. Schr{\"o}der-Preikschat and J. Teich",

booktitle = "Architecture of Computing Systems- ARCS 2016",

note = "Architecture of Computing Systems, ARCS 2016 : 29th International Conference ; Conference date: 04-04-2016 Through 07-04-2016",

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Kritchallo, V, Braithwaite, B, Vermij, E, Bertels, K & Al-Ars, Z 2016, Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. in F Hannig, JMP Cardoso, T Pionteck, D Fey, W Schröder-Preikschat & J Teich (eds), Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Lecture Notes in Computer Science, vol. 9367, Springer, Cham, pp. 251-262, Architecture of Computing Systems, ARCS 2016, Nuremberg, Germany, 4/04/16. https://doi.org/10.1007/978-3-319-30695-7_19

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. / Kritchallo, Valery; Braithwaite, Billy; Vermij, Erik et al.
Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. ed. / F. Hannig; J.M.P. Cardoso; T. Pionteck; D. Fey; W. Schröder-Preikschat; J. Teich. Cham: Springer, 2016. p. 251-262 (Lecture Notes in Computer Science; Vol. 9367).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

AU - Kritchallo, Valery

AU - Braithwaite, Billy

AU - Vermij, Erik

AU - Bertels, Koen

AU - Al-Ars, Zaid

PY - 2016

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N2 - We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.

AB - We present a novel approach to tradeo accuracy against the degree of parallelization for the Canny edge detector, a well-known image-processing algorithm. At the heart of our method is a single top-level image-slicing loop incorporated into the sequential algorithm to process image segments concurrently, a parallelization technique allowing for breaks in the computational continuity in order to achieve high performance levels. By using the delity slider, a new approximate computing concept that we introduce, the user can exercise full control over the desired balance between accuracy of the output and parallel performance. The practical value and strong scalability of the presented method is demonstrated by extensive benchmarks performed on threeevaluation platforms, showing speedups of up to 7x for an accuracy of 100% and up to 19x for an accuracy of 99% over the sequential version, as recorded on an Intel Xeon platform with 14 cores and 28 hardware threads.

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BT - Architecture of Computing Systems- ARCS 2016

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Kritchallo V, Braithwaite B, Vermij E, Bertels K, Al-Ars Z. Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector. In Hannig F, Cardoso JMP, Pionteck T, Fey D, Schröder-Preikschat W, Teich J, editors, Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Cham: Springer. 2016. p. 251-262. (Lecture Notes in Computer Science). doi: 10.1007/978-3-319-30695-7_19

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

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