BTI analysis of SRAM write driver

IO Agbo; M Taouil; S Hamdioui; P Weckx; S Cosemans; F Catthoor

doi:10.1109/IDT.2015.7396744

BTI analysis of SRAM write driver

IO Agbo, M Taouil, S Hamdioui, P Weckx, S Cosemans, F Catthoor

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

6 Citations (Scopus)

Abstract

Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.

Original language	English
Title of host publication	Proceedings of the 10th International Design and Test Symposium, IDT 2015
Editors	F Kurdahi, S Mir, MO Yu
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	100-105
Number of pages	6
ISBN (Print)	978-1-4673-9993-4
DOIs	https://doi.org/10.1109/IDT.2015.7396744
Publication status	Published - 2015
Event	IDT 2015: 10th International Design and Test Symposium - Amman, Jordan Duration: 14 Dec 2015 → 16 Dec 2015 Conference number: 10

Conference

Conference	IDT 2015
Country/Territory	Jordan
City	Amman
Period	14/12/15 → 16/12/15

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10.1109/IDT.2015.7396744

Cite this

@inproceedings{a60f7b8b48ad438e8b495f6ff1a92942,

title = "BTI analysis of SRAM write driver",

abstract = "Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.",

author = "IO Agbo and M Taouil and S Hamdioui and P Weckx and S Cosemans and F Catthoor",

year = "2015",

doi = "10.1109/IDT.2015.7396744",

language = "English",

isbn = "978-1-4673-9993-4",

pages = "100--105",

editor = "F Kurdahi and S Mir and MO Yu",

booktitle = "Proceedings of the 10th International Design and Test Symposium, IDT 2015",

publisher = "IEEE Society",

note = "IDT 2015 : 10th International Design and Test Symposium ; Conference date: 14-12-2015 Through 16-12-2015",

}

TY - GEN

T1 - BTI analysis of SRAM write driver

AU - Agbo, IO

AU - Taouil, M

AU - Hamdioui, S

AU - Weckx, P

AU - Cosemans, S

AU - Catthoor, F

N1 - Conference code: 10

PY - 2015

Y1 - 2015

N2 - Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.

AB - Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.

U2 - 10.1109/IDT.2015.7396744

DO - 10.1109/IDT.2015.7396744

M3 - Conference contribution

SN - 978-1-4673-9993-4

SP - 100

EP - 105

BT - Proceedings of the 10th International Design and Test Symposium, IDT 2015

A2 - Kurdahi, F

A2 - Mir, S

A2 - Yu, MO

PB - IEEE Society

CY - Piscataway

T2 - IDT 2015

Y2 - 14 December 2015 through 16 December 2015

ER -

BTI analysis of SRAM write driver

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