Circuit monitoring techniques have been adopted widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. For cost and complexity reasons, these techniques are usually implemented by means of performance monitors allowing fast performance evaluation during production. In this paper, we demonstrate the limitations of performance monitoring methodologies in terms of accuracy and effectiveness. Silicon measurements of a nanometric FD-SOI device show that the required design margin is above 10% of the clock cycle, which leads to unacceptable waste of
power.
Original languageEnglish
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
EditorsJürgen Teich
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1018-1019
Number of pages2
ISBN (Electronic)978-3-9815370-7-9
ISBN (Print)978-3-9815370-6-2
Publication statusPublished - 2016
Event2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: 14 Mar 201618 Mar 2016

Conference

Conference2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Abbreviated titleDATE 2016
CountryGermany
CityDresden
Period14/03/1618/03/16

    Research areas

  • Monitoring, Temperature measurement, Temperature sensors, Performance evaluation, Semiconductor device measurement, Frequency measurement, Timing

ID: 10710398