The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

Original languageEnglish
Title of host publication48th European Solid-State Device Research Conference, ESSDERC 2018
EditorsFrank Ellinger, Thomas Mikolajick, Pawel Grybos
PublisherEditions Frontieres
Pages246-249
Volume2018-September
ISBN (Electronic)9781538654019
DOIs
Publication statusPublished - 2018
Event48th European Solid-State Device Research Conference, ESSDERC 2018 - Dresden, Germany
Duration: 3 Sep 20186 Sep 2018

Conference

Conference48th European Solid-State Device Research Conference, ESSDERC 2018
CountryGermany
CityDresden
Period3/09/186/09/18

ID: 47549251